Chip Multiprocessor Traffic Models Providing Consistent Multicast and Spatial Distributions

Abstract

Chip multiprocessors (CMPs) have become the center of attention in recent years. They consist of multiple processor cores on a single chip. These cores are connected on-chip by a bus or, if many cores are involved, by an appropriate network. To investigate how a multicore processor behaves dependent on the chosen network-on-chip topology, a corresponding model must be established for performance evaluation. Modeling and simulating the entire system would lead to high model complexity. Thus, it is more reasonable to exclude the cores and to simply model stochastically the detached network. The cores are replaced by traffic generators which must provide reasonable CMP traffic. It usually consists of multicasts and a particular spatial distribution. Because the traffic is not known exactly, both multicasts and spatial traffic are described as stochastic distributions for model input. The easiest way is to specify the spatial distribution of the traffic and the kind of multicasts independently of each other. However, not all multicast distributions can be achieved with a particular desired spatial distribution and vice versa. It is therefore important to check for the compatibility of the spatial distribution and the multicasts that the modeler is willing to investigate. Such a compatibility check is provided by the algorithm presented in this paper. It prevents inconsistent traffic parameters while modeling.

Keywords

stochastic traffic modeling network-on-chip multicore processor multicast distribution spatial traffic distribution

Get full access to this article

View all access options for this article.

References

Dally, W.J. and S. Lacy. 1999. VLSI Architecture: Past, Present, and Future . In Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI, 232-241.

Guerrier, P. and A. Grenier. 2000. A Generic Architecture for On-Chip Packet-Switched Interconnections . In Proceedings of IEEE Design Automation and Test in Europe (DATE 2000), IEEE Press, 250-256.

Alderighi, M. , F. Casini , S. D'Angelo , D. Salvi , and G.R. Sechi. 2002. A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications . In Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA'02) , 302-306.

Pande, P.P. , C.S. Grecu , A. Ivanov , and R.A. Saleh. 2003. Switch-Based Interconnect Architecture for Future Systems on Chip . In Proceedings of the SPIE, vol. 5117, 228-237.

Lahiri, K. , S. Dey , and A. Raghunathan. 2001. Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures . In Proceedings of the 14th International Conference on VLSI Design (VLSID '01), IEEE Press, 29-35.

Wingard, D. 2001. MicroNetwork-Based Integration for SoCs . In Proceedings of the Design Automation Conference (DAC 2001), ACM, 673-677.

Wiklund, D. and D. Liu . 2003. SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems . In Proceedings of the 17th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2003), IEEE Press, 78-85.

Kumar, S. , A. Jantsch , J.-P. Soininen , M. Forsell , M. Millberg , J. Öberg , K. Tiensyrjä , A. Hemani. 2002. A Network on Chip Architecture and Design Methodology . In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02), 105- 112.

Bononi, L. and N. Concer. 2006. Simulation and Analysis of Network on Chip Architectures: Ring, Spidergon and 2D Mesh . In Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2006), ACM, New York, 154-159.

10.

Azimi, M. , N. Cherukuri , D. Jayasimha , A. Kumar , P. Kundu , S. Park , I. Schoinas , and A.S. Vaidya. 2007. Integration Challenges and Tradeoffs for Tera-scale Architectures . Intel Technology Journal 11(3), 173-184.

11.

Lee, S.-J. , S.-J. Song , K. Lee , J.-H. Woo , S.-E. Kim , B.-G. Nam , and H.-J. Yoo . 2003. An 800MHz Star-Connected On-Chip Network for Application to Systems on a Chip . In Proceedings of 2003 IEEE International Solid-State Circuits Conference (ISSCC 2003), IEEE Press , 468-475.

12.

Sánchez, J.L. and J.M. García. 2000. Dynamic Reconfiguration of Node Location in Wormhole Networks . Journal of Systems Architecture 46(10), 873-888.

13.

Bertozzi, D. , A. Jalabert , S. Murali , R. Tamhankar , S. Stergiou , L. Benini , and G. De Micheli. 2005. NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip . IEEE Transactions on Parallel and Distributed Systems 16(2), 113-129.

14.

Ching, D. , P. Schaumont , and I. Verbauwhede. 2004. Integrated Modeling and Generation of a Reconfigurable Network-On-Chip . In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 139-145.

15.

Tutsch, D. , D. Lüdtke , A. Walter , and M. Kühm. 2005. CINSim - A Component-Based Interconnection Network Simulator for Modeling Dynamic Reconfiguration . In Proceedings of the 12th International Conference on Analytical and Stochastic Modelling Techniques and Applications (ASMTA 2005)1 Riga, IEEE/SCS, 132-137.

16.

Tutsch, D. and D. Lüdtke. 2007. Spatial Distributions versus Multicast Distributions: Traffic Modeling of Chip Multiprocessor Networks . In Proceedings of the International Symposium on Performance Evaluation of Computer and Telecommunication Systems (SPECTS 2007)1 San Diego, SCS, Erlangen, 512-520.

17.

Tutsch, D. 2006. Performance Analysis of Network Architectures. Springer Verlag, Berlin.

18.

Tutsch, D. and G. Hommel. 2006. High Performance Low Cost Multicore NoC Architectures for Embedded Systems . In Proceedings of the International Workshop on Embedded Systems - Modeling, Technology and Applications, Springer-Verlag, Berlin, 53-62.

19.

Lüdtke, D. , D. Tutsch , A. Walter , and G. Hommel. 2005. Improved Performance of Bidirectional Multistage Interconnection Networks by Reconfiguration . In Proceedings of 2005 Design, Analysis, and Simulation of Distributed Systems (DASD 2005)1 San Diego, SCS, Erlangen, 21-27.

20.

Lüdtke, D. and D. Tutsch. 2006. Combining Spatial and Multicast Traffic Distributions for Stochastic Modeling and Simulation of Networks-on-Chip . In M. Becker, H. Szczerbicka, eds., Proceedings of the 19th Symposium on Simulation Technique (ASIM 2006), SCS, Erlangen, 241-246.