Modeling and simulation of an eight-bit auto-configurable successive approximation register analog-to-digital converter for cardiac and neural implants

Abstract

An analog-to-digital converter (ADC) is a critical block of the sensing unit of all implants and for measurements of various biophysiological signals that cover distinct portions of the frequency spectrum and signal bandwidths. However, the conventional methodology of direct transistor-level implementation of the ADC for any application does not guarantee the accuracy to meet the desired specifications. For this purpose, the behavioral modeling approach facilitates the designer to set up an environment to extract various electric and dynamic parameters with a good level of accuracy. Based on this, behavioral modeling of a new architecture of an eight-bit auto-configurable successive approximation register (SAR) ADC has been proposed in this paper for application in both cardiac and neural implants, such as pacemakers, deep brain stimulators, etc. All the building blocks of the SAR ADC have been modeled in such a way that the ADC can operate either in the voltage mode or the current mode and the various non-idealities, such as clock jitter, clock feedthrough, and thermal and flicker noise, among others, have been incorporated into the design to make it as realistic as possible and estimate the response of the ADC with high accuracy. Based on the simulations for both ideal and non-ideal scenarios, it is observed that the proposed eight-bit auto-configurable SAR ADC works efficiently for applications in both cardiac and neural implants and achieves a signal-to-noise ratio as high as 48.943 dB and effective number of bits of 7.838 bits with very low distortion of only −62.549 dB.

Keywords

Analog-to-digital converter behavioral modeling cardiac implant configurable system neural implant successive approximation register

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