Why we should use Min Max DEVS for modeling and simulation of digital circuits

The delay is a very important element in modeling hardware behavior, and is realized in many hardware description languages such as ADLIB-SABLE, Verilog, and VHDL. The state of the art on hardware delay identifies four classes. In the first class, mean values are used as a precise delay element in the simulation; we found it in VHDL (VHSIC (very high speed integrated circuit) Hardware Description Language), where a single value is utilized to characterize the transport delay. In the second class, the delay is represented by an interval min max, meaning that the delay value is precisely unknown and every value in the interval can represent a possible value for the actual delay. In the third class, a delay is expressed in the form of a stochastic distribution. Fuzzy models of delay constitute the last class. In reality, it is very difficult, if not impossible, to obtain a precise value of the delay; there are many reasons for that: temperature, voltage, variation in the manufacturing process, and other environment parameters. The Min Max DEVS formalism allows an efficient design of the min max delay by proposing a definition of the lifetime function based on time interval. Moreover, its simulation semantics allows the simulation of Min Max DEVS models with only one replication, allowing us to conclude whether the min max delay is too large or exact simulations cannot be obtained. In this paper, we propose to highlight the Min Max DEVS formalism through examples from digital circuits, after having recalled its basic definitions and its simulation semantics. Then, we compare the simulation results obtained with those provided by the well-known tool in the field of digital circuits, Verilog, using the same examples.