Behavioral Simulation of Array Processors in the APES Environment

Abstract

APES is an integrated, flexible CAD environment developed for behavioral design, simulation and evaluation of array processor architectures. This paper discusses in detail the core of the system, i.e., the behavioral simulator. This is an interactive subsystem which allows one to set up and run the simulation of the array using the definition of the array architecture supplied by the user. This task computes the output results of the whole array, of each processing element and of each functional unit. The concept of time is also defined and handled by the simulator so to allow subsequent performance evaluation. Functions are available for tracing, for inserting break- points, for step-by-step execution and for selection of display format. The simulator interacts with the other modules of APES (e.g., the Fault Injector, the Reconfiguration Manager) and produces results which can also be post-processed by other modules of APES (e.g., the Diagnostic Evaluator) to aid the designer in evaluating particular characteristics of the architecture.

Get full access to this article

View all access options for this article.

References

S.Y. Kung , VLSI array processors, Prentice Hall, 1988

H.T. Kung , S.C. Lo , S.N. Jean , J.N. Kwang , "Wavefront array processors - Concepts and Implementation", IEEE Computer Magazine , July 1987

"IEEE Design and Test of Computers," Special Issue on VHDL, April 1986

R. Negrini , M. Sami , R. Stefanelli , Fault Tolerance through Reconfiguration for VLSI and WSI Arrays, The MIT Press, 1989

F. Distante , R. Negrini , V. Piuri , "Simulated annealing for Defect tolerance in two-dimensional Arrays ", IFIP Proc. Workshop on Wafer Scale Integration , Brunel, U.K., 1987

F. Distante et al., "APES - Implementation of a CAD tool for Array processor Design: Textual Definition versus Graphic Description ", Proc. EUROMICRO 89, Cologne , Germany, Sept. 1989

F. Distante , V. Piuri "APES: an evaluation environment of fault-tolerance capabilities of array processors", Proc. 1989 IEEE Workshop and Defect and Fault Tolerance in VLSI Systems, Tampa, Florida , Oct. 1989

F. Distante , V. Piuri "APES: an integrated system for behavioral design simulation and evaluation of array processors", Proc. ICCD 88, Rye Brook, New York, Oct. 1988