A Framework for Distributed VLSI Simulation on a Network of Workstations

Abstract

A distributed framework for logic simulation is presented. Switch-level simulation has been mapped to a distributed platform using a network of workstations on an Ethernet bus. Model parallelism is used with preprocessing to partition the circuit to be simulated among the processors. The simulation algorithm is decoupled from the communication layers to ensure easy portability. We have proposed a high level pipelining scheme with multiple buffers to overcome the effects of a low bandwidth network. Speedups of up to 4.1 with 5 processors have been obtained for medium sized ISCAS benchmark circuits. The speedups achieved using distributed simulation are very close to that obtained by the same switch-level simulator imple mented on a shared memory parallel machine. Novel techniques to improve the performance of distributed simulation have also been implemented on a shared memory parallel machine.

Keywords

Parallel processing net works distributed simulation VLSI logic simulation performance algorithm

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