Programming the Adapteva Epiphany 64-core network-on-chip coprocessor

Abstract

Energy efficiency is the primary impediment in the path to exascale computing. Consequently, the high-performance computing community is increasingly interested in low-power high-performance embedded systems as building blocks for large-scale high-performance systems. The Adapteva Epiphany architecture integrates low-power RISC cores on a 2D mesh network and promises up to 70 GFLOPS/Watt of theoretical performance. However, with just 32 KB of memory per eCore for storing both data and code, programming the Epiphany system presents significant challenges. In this paper we evaluate the performance of a 64-core Epiphany system with a variety of basic compute and communication micro-benchmarks. Further, we implemented two well known application kernels, 5-point star-shaped heat stencil with a peak performance of 65.2 GFLOPS and matrix multiplication with 65.3 GFLOPS in single precision across 64 Epiphany cores. We discuss strategies for implementing high-performance computing application kernels on such memory constrained low-power devices and compare the Epiphany with competing low-power systems. With future Epiphany revisions expected to house thousands of cores on a single chip, understanding the merits of such an architecture is of prime importance to the exascale initiative.

Keywords

Network-on-chip Epiphany stencil parallella matrix-matrix multiplication

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References

Adapteva (2012a) Epiphany architecture reference manual. Available at: http://www.adapteva.com/wp-content/uploads/2012/12/epiphany_arch_reference_3.12.12.18.pdf

Adapteva (2012b) Epiphany technical reference documents. Available at: http://www.adapteva.com/all-documents

Bell

Edwards

Amann

. (2008) Tile64-processor: A 64-core soc with mesh interconnect. In: Proceedings of the Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers. San Francisco, CA, 3–7 February 2008, pp. 88–598.

Bergman

Borkar

Campbell

. (2008) Exascale computing study: Technology challenges in achieving exascale systems. Technical Report 15. Defense Advanced Research Projects Agency Information Processing Techniques Office (DARPA IPTO), USA.

Beyer

Stotzer

Hart

de Supinski

(2011) OpenMP for accelerators. In: Proceedings of the 7th International Workshop on OpenMP. Chicago, IL, 13–15 June 2011, pp. 108–121. Chicago, IL: Springer.

Buttari

Dongarra

Langou

JKJ

. (2006) Exploiting mixed precision floating point hardware in scientific computations. In: Proceedings of the High Performance Computing Workshop. Cetraro, Italy, 2006, pp. 19–36.

Cannon

(1969) A cellular computer to implement the kalman filter algorithm. Technical report, Defense Technical Information Center, USA.

Choi

Walker

Dongarra

(1994) Pumma: Parallel universal matrix multiplication algorithms on distributed memory concurrent computers. Concurrency: Practice and Experience 6(7): 543–570.

Datta

Kamil

Williams

. (2009) Optimization and performance modeling of stencil computations on modern microprocessors. SIAM review 51(1): 129–159.

10.

Dongarra

(2006) The impact of multicore on math software and exploiting single precision computing to obtain double precision results. In: Guo

Yang

Di Martino

Zima

Dongarra

Tang

(eds) Parallel and Distributed Processing and Applications, Lecture Notes in Computer Science, volume 4330. Heidelberg: Springer Berlin, p. 2.

11.

Heinecke

Vaidyanathan

Smelyanskiy

. (2013) Design and implementation of the linpack benchmark for single and multi-node systems based on intel® xeon phi coprocessor. In: Proceedings of the 27th IEEE International Parallel & Distributed Processing Symposium. Boston, MA, 20–24 May 2013, pp. 126–137.

12.

Igual

Ali

Friedmann

. (2012) Unleashing the high-performance and low-power of multi-core dsps for general-purpose hpc. In: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis. Salt Lake City, UT, 11–15 November 2012, p. 26. Washington, DC: IEEE.

13.

Mattson

Riepen

Lehnig

. (2010) The 48-core scc processor: the programmer’s view. In: Proceedings of the 2010 ACM/IEEE International Conference for high-performance Computing, Networking, Storage and Analysis. New Orleans, LA, 13–19 November 2010, pp. 1–11. Washington, DC: IEEE.

14.

Mattson

Van der Wijngaart

Frumkin

(2008) Programming the Intel 80-core network-on-a-chip terascale processor. In: Proceedings of the 2008 ACM/IEEE conference on Supercomputing. Austin, TX, 15–21 November 2008, p. 38. Piscataway, NJ: IEEE Press.

15.

In: 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems. Fiuggi, Italy, 8–14 July 2012.

16.

Mitra

Johnston

Rendell

. (2013) Use of SIMD vector operations to accelerate application code performance on low-powered ARM and Intel platforms. In: Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW). Boston, MA, 20–24 May 2013, pp. 1107–1116. Washington, DC: IEEE.

17.

NVIDIA (2014) NVIDIA Tegra K1 Processor. Available at: http://www.nvidia.com/object/tegra-k1-processor.html (accessed 17 August 2015).

18.

Sapir

(2012) Scalable parallel multiplication of big matrices. Available at: http://www.adapteva.com/whitepapers/scalable-parallel-multiplication-of-big-matrices/ (accessed 17 August 2015).

19.

Serres

Anbar

Merchant

El-Ghazawi

(2011) Experiences with upc on tile-64 processor. In: Aerospace Conference, 2011 IEEE. Montana, USA, 5–12 March 2011, pp. 1–9. Washington, DC: IEEE.

20.

Stotzer

Jayaraj

Ali

. (2013) Openmp on the low-power TI keystone II ARM/DSP system-on-chip. In: Proceedings of the OpenMP in the Era of Low Power Devices and Accelerators. Canberra, ACT, 16–18 September 2013, pp. 114–127. Springer.

21.

Van De Geijn

Watts

(1997) Summa: Scalable universal matrix multiplication algorithm. Concurrency-Practice and Experience 9(4): 255–274.

22.

Vangal

Howard

Ruhl

. (2008) An 80-tile sub-100-w teraflops processor in 65-nm cmos. Solid-State Circuits, IEEE Journal of 43(1): 29–41.

23.

Wittmann

Hager

Wellein

(2010) Multicore-aware parallel temporal blocking of stencil codes for shared and distributed memory. In: Proceedings of the IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW). Atlanta, GA, 19–23 April 2010, pp. 1–7. Washington, DC: IEEE.

24.

ZedBoard (2012) ZedBoard development kit. Available at: http://www.zedboard.org/product/zedboard