Stability analysis of a proposed charge balance A/D converter for load cell signal acquisition

Abstract

This article proposed and discussed a kind of sigma-delta A/D converter for load cell signal acquisition, which uses improved charge balance technique. The traditional charge balance sigma-delta A/D converter is stable if and only if the magnitude of the input signal current is less than one half the magnitude of the reference current, which limits the accuracy improvement of load cell. This article examined the stability of an improved version of the charge balance sigma-delta A/D converter. The proposed converter can be designed to be stable for input signals as large as the reference, which is helpful to improve load cell’s measurement accuracy.

Keywords

A/D converter signal acquisition circuit stability analysis frequency domain analysis load cell

Introduction

The charge balance–based sigma-delta (SD) A/D converter is a well-known high-accuracy analog-to-digital converter,¹ which is used in measurement circuits of load cells, force transducers, and pressure sensors widely. Due to more and more high-accuracy requirement for weighing and force measuring, there are a number of research works focused on improving the A/D converters for higher measure precision,^2–4 and some researchers also used it on different sensors.^5,6 However, there is a limitation that the traditional charge balance A/D converter may be unstable during data acquisition under certain conditions. There have been several analyses and methods introduced to improve its performance,^7–10 such as a closed-loop control system designed by Bharti et al.⁹ to increase output voltage stability and a single opamp third-order SD modulator designed by Chao¹⁰ for high-resolution applications. But all of these methods/architectures/models are complicated and expensive. This report discussed the design and theory of a novel improved converter. The proposed charge balance technique can achieve 24-bit performance, so it is suitable for low-level unipolar or bipolar signals in signal acquisition circuit of load cell, which can be overcome the limitation of traditional charge balance A/D converter.

Charge balance ΔΣ A/D converter

The proposed converter is identical to the traditional version except for one important attribute. Figure 1 is a schematic diagram that illustrates the improved charge balance technique. There is one component of the schematic in Figure 1 that differs from the traditional converter which is the voltage v_ramp that is used as the comparator reference. The traditional converter uses a constant voltage of 0 V as the reference, whereas v_ramp in the proposed converter is a saw tooth waveform (Figure 2). The slope of the ramp voltage is denoted by m_ramp (Figure 2). In all aspects other than the comparator reference voltage, the rules of operation of the proposed converter are identical to the traditional version. In both converters, the integrator capacitor is charged and discharged by i_sig and I_ref during two phases, and the magnitude of the input voltage is determined from the measured lengths of the charging and discharging times. In the proposed converter, however, the transition between phases 1 and 2 occurs when the falling v_out ramp crossed the rising v_ramp ramp, rather than when v_out reaches 0 V. Figure 3 illustrates a typical conversion cycle. The variables (v_i and v_f) represent the initial and final values of v_out for a single conversion cycle. The variable t_x represents the length of phase one, and the total length of the conversion cycle is T₀. The value of v_out at the transition between phases is denoted by v_x.

Figure 1.

Simplified schematic diagram of proposed charge balance A/D converter.

Figure 2.

Plot of saw tooth voltage used for comparator reference.

Figure 3.

Graph of integrator output voltage during typical conversion cycle.

Analyses and discussion

Stability analysis in time domain

In Figure 3, the slopes of v_out during the two phases are governed by i_sig and I_ref that combine to form the total current into the capacitor. The integrator output voltage during phase 1, $v_{out} = - (i_{sig} / C) + (I_{ref} / C) t + v_{i}$ , and the integrator output voltage during phase 2, $v_{out} = - (i_{sig} / C) (t - t_{x}) + v_{x}$ . The two components of the slope of this voltage are identical to those for the traditional converter. Figure 4 indicates the manner in which the slope components $m_{sig} = - (i_{sig} / C)$ and $m_{ref} = - (I_{ref} / C)$ contribute to the slopes of v_out during the two phases.

Figure 4.

Illustration of slopes of v_out during typical conversion cycle.

For an arbitrary set of constant slopes m_sig, m_ref, and m_ramp, an equation may be obtained that relates the values of v_i and v_f. The first step is to obtain the following expressions for v_x: $v_{x} = v_{i} + t_{x} (m_{sig} + m_{ref})$ and $v_{x} = t_{x} (m_{ramp})$ . Then, v_out for phase 2, an equation may be evaluated at T₀ to give an expression for v_f: $v_{f} = v_{x} + (T_{0} - t_{x}) m_{sig}$ . Finally, the relation of the values of v_i and v_f is obtained by substituting above three equations

v_{f} = v_{i} (1 - \frac{m_{ref}}{m_{sig} + m_{ref} - m_{ramp}}) + T_{0} m_{sig}

(1)

Equation (1) gives the value of v_out at the end of a conversion period in terms of its value at the beginning of the conversion period when the input signal is constant. This equation may be used recursively to generate a sequence of peaks in v_out that would result from an arbitrary initial value. The recursion can be written in a simpler form

v (k + 1) = bv (k) + c, k = 0, 1, 2, \dots

(2)

The values of the peaks of v_out are represented by v(k), and the constants b and c correspond to the following terms from equation (1)

b = 1 - \frac{m_{ref}}{m_{sig} + m_{ref} - m_{ramp}}

(3)

c = T_{0} m_{sig}

(4)

Here, c is identical to the corresponding term in the difference equation for the traditional converter, but b is different. The above difference equation generates a sequence of values that converges to an equilibrium value when the converter is stable. All peak values of v_out equal this value when the system is at equilibrium. The equilibrium value of peak voltage (v_e) may be calculated from equation (2) for a given b and c by setting both v(k + 1) and v(k) to v_e, $v_{e} = {bv}_{e} + c$ ; then, $v_{e} = (T_{0} m_{sig} / m_{ref}) (m_{sig} + m_{ref} - m_{ramp})$ . Compared to the equilibrium value of the traditional converter, $v_{e} = T_{0} m_{sig} / m_{ref} (m_{sig} + m_{ref})$ , they are identical except for the rightmost multiplying factors within parenthesis. The following relationships are useful in comparing the magnitudes of v_e for the two converters: m_sig > 0, m_ref < 0, m_sig + m_ref < 0, and m_ramp > 0. These inequalities allow direct comparison of the equilibrium values for the traditional and proposed converters: v_e(proposed) > v_e(traditional).

Figure 5 is a plot of v_out during equilibrium for a hypothetical set of parameters for both the traditional and proposed converters. The figure also shows that the equilibrium peak voltage of the proposed converter is greater than that of the traditional converter for the same input signal. In fact, the function v_out for the proposed converter is greater than v_out of the traditional converter by a constant difference (v_x) over the entire conversion period. This is a consequence of the equality of the corresponding slopes of v_out for the two converters. Each converter used the same reference current, which determined the reference slope m_ref. The input current i_sig, which determined the slope m_sig, also is identical for the two converters for this example.

Figure 5.

Comparison of conversion cycle for traditional and proposed converters.

In Figure 5, although the integrator output voltage is greater for the proposed converter, the time of the transition between the two phases (t_x) is the same for both converters.

Because of the recursive manner in which peaks of v_out are produced by the proposed converter in equation (2), there are certain conditions for which the converter is not stable. Successive evaluation of equation (2) using an arbitrary initial value v(0) yields the following

\begin{matrix} v (1) = b \cdot v (0) + c (2) = b^{2} v (0) + bc + c \\ ⋮ (N) = b^{N} v (0) + b^{N - 1} c + b^{N - 2} c + \dots + b^{2} c + bc + c \\ \Rightarrow v (N) = b^{N} v (0) + c \sum_{n = 0}^{N - 1} b^{n} \end{matrix}

(5)

Equation (5) is an expression for the peak in v_out after N conversion cycles, given that the input voltage is constant and that the value of v_out at the start of the first cycle is v(0). As for both converters, the following condition must hold for stable sequences: $lim_{N \to \infty} {v (N)} < \infty$ . The sequence of equation (5) diverges unless $lim_{N \to \infty} {v (N)} < \infty$ is satisfied. Both the summation in equation (5) and other term in the sum, b^Nv(0), converge uniformly to finite limits if and only if the following condition holds: |b| < 1. The following alternate expression of the condition for stability is obtained by substitution of equation (3) into |b|< 1; then, the inequality for stability condition is obtained

m_{sig} < m_{ramp} - \frac{1}{2} m_{ref}

(6)

By following the same procedure, the corresponding stability condition for the traditional converter given (m_ref is negative) can be obtained

m_{sig} < - \frac{1}{2} m_{ref}

(7)

The inequalities of equations (6) and (7) differ only in the m_ramp term that appears in the equation for the proposed converter. The stability constraint of equation (7) requires that the input signal current i_sig be less than one half the magnitude of the reference current I_ref for the traditional converter. However, the presence of the m_ramp term in equation (6) raises the limit of allowable input signal current for the proposed converter. Thus, the proposed converter can measure higher input currents than the traditional converter without becoming unstable.

If it is desired to measure currents as large as the reference current I_ref, then equation (6) must hold for slopes m_sig as great as −m_ref. Substitution of this value for m_sig into equation (6) yields the following condition

m_{ramp} > \frac{1}{2} | m_{ref} |

(8)

The inequality of equation (8) must be satisfied if the proposed converter is to be stable for input signals as large as the reference. In other words, the slope of the comparator reference voltage v_ramp must be greater than one half the magnitude of the slope m_ref if full-scale input signals (relative to the reference) are to be measured. If a suitably steep ramp is used, full-scale signals may be measured, that is, the proposed converter can be stable for duty cycles as high as unity.

Stability analysis in frequency domain

A frequency domain representation of the difference equation (2) provides additional insight into the stability of the proposed converter. A slightly different version of the equation is given as $v [k] = bv [k - 1] + c$ . This equation may be modeled by the simple discrete-time system shown in Figure 6.

Figure 6.

Block diagram of difference equation.

The term z⁻¹ in the figure denotes a unit delay. The input x^[k] is assumed to be a step function of amplitude c, that is, x^[k] = c u^[k]. The sequence x^[k] is used as an input to the discrete-time model only to supply the constant term c present in the difference equation. The output v^[k] equals the sequence of peaks in v_out produced by any initial value v^[0]. The equivalent difference equation is given as $v [k] = bv [k - 1] + x [k]$ , $x [k] = cu [k]$ . The corresponding system function is obtained by taking the z-transform

\Rightarrow \frac{V (z)}{X (z)} = \frac{z}{(z - b)}

(9)

The system function of equation (9) has a pole at z = b. This pole is on the real axis because b is a real number (from equation (3)). Figure 7 is a plot of the poles and zeros of the system function.

Figure 7.

Pole–zero plot of system function of equation (9).

As the figure indicates, the function has a zero at the origin. This single zero is a manifestation of the single unit delay in the output of the composite system. Poles and zeros at the origin reflect shifts in time, but they do not contribute to the magnitude of the system function; therefore, they do not affect the stability of the system. However, the location of the pole at z = b does affect stability. The magnitudes of all system poles must be less than unity if a system is to be stable; thus, all poles must lie inside the unit circle. This implies that the system of equation (9) is stable if and only if the magnitude of b is less than one, which is equivalent to the stability condition by time domain analysis. The location of the pole on the real axis of the z-plane may be expressed as a function of different parameters, including the various components of slope used in the foregoing analysis. Alternately, the pole location may be expressed in terms of relative input i and a system parameter K. The relative input is defined as the ratio of the input current to the reference current: $i = I / I 0 = | i_{sig} / I_{ref} | = - m_{sig} / m_{ref}$ . The system parameter K can be described as a function of the reference and ramp currents: $K = | I_{ref} / i_{ramp} | = - m_{ref} / m_{ramp}$ . The equation describing b in terms of slopes (equation (3)) may be modified in terms of K and i as follows

b = \frac{- i + \frac{1}{K}}{- i + 1 + \frac{1}{K}} = \frac{1 - Ki}{1 + K (1 - i)}

(10)

Equation (10) describes the pole location of the proposed converter. As noted in an analysis before, when K is less than or equal to two, the converter is stable for input signals as large as the reference.

As long as the slope m_ramp meets the requirement of equation (8), the converter will converge toward a state of equilibrium from any initial state. However, some characteristics of the convergence depend on the relative values of m_ramp and m_sig. In the examples shown in Figures 3 –5, the ramp slopes m_ramp are greater than the signal slopes m_sig, but this is not necessarily true for all stable configurations. In particular, the ramp slope may be less than the magnitude of the reference slope: $(1 / 2) | m_{ref} | < m_{ramp} < | m_{ref} |$ . If this inequality is true, then the condition of equation (8) is satisfied, and the converter is stable for input currents as large as the reference, and this inequality implies that the signal slope exceeds the ramp slope for some subset of stable input signal magnitudes: $m_{ramp} < m_{sig} < | m_{ref} |$ . Figure 8 shows an example for which these conditions apply.

Figure 8.

Illustration of slopes of v_out with signal slope greater than ramp slope.

The values of m_ramp and m_sig affect the convergence of the converter because they influence the value of the coefficient b of equation (3) that is used in the difference equation (2). As outlined in the preceding, b also specifies the location of the pole of the discrete-time system that models the converter. The following relationships may be derived from equation (3):

If $m_{sig} < m_{ramp}$ , then b > 0;

If $m_{ramp} < m_{sig} < m_{ramp} + | m_{ref} |$ , then b < 0;

If $m_{ramp} = m_{sig}$ , then b = 0.

As the system converges, each successive v_out peak draws closer to the equilibrium value than the previous peak. If b is nonzero, its sign determines whether v_out overshoots the equilibrium value with each iteration. When $m_{sig} < m_{ramp}$ and b is positive, there is no overshoot. This condition is illustrated in Figure 9.

Figure 9.

Conversion cycles with ramp slope greater than signal slope.

The figure depicts two different v_out curves, v_out1 at equilibrium and v_out2 converging to equilibrium. Both the initial and final values of v_out1 equal the equilibrium peak value, v_e. The initial value of v_out2 is greater than the equilibrium value by an amount denoted by Δv_i. The peak value of v_out2 at the end of the conversion period is also greater than the equilibrium value by the amount Δv_f. The magnitude of Δv_f is less than the magnitude of Δv_i because the system is stable. Moreover, the sign of Δv_i is the same as the sign of Δv_f, indicating that v_out2 does not overshoot the equilibrium value for this example. This is a consequence of the positive sign of b and the fact that the ramp slope exceeds the signal slope. The sequence of peaks of v_out converges to the equilibrium value from above in this example. Figure 10 illustrates this process for several successive conversion periods.

Figure 10.

Typical convergence with ramp slope greater than signal slope.

When the signal slope exceeds the ramp slope and b is negative, the peak value of v_out overshoots the equilibrium value with each conversion cycle. This condition is illustrated in Figure 11.

Figure 11.

Conversion cycles with signal slope greater than ramp slope.

Two different v_out curves are shown again, v_out1 at equilibrium and v_out2 converging to equilibrium. The initial value of v_out2 again exceeds the equilibrium value by Δv_i, and the peak value of v_out2 at the end of the conversion period differs from the equilibrium value by the amount Δv_f. As shown in Figure 9, the magnitude of Δv_f is less than the magnitude of Δv_i, but the sign of Δv_i is negative, indicating that v_out2 overshoots the equilibrium value. This occurs because the ramp slope is smaller than the signal slope, causing b to be negative. The sequence of peaks of v_out converges to the equilibrium value in an oscillatory manner in this example. Figure 12 illustrates this behavior for a few conversion periods.

Figure 12.

Typical convergence with signal slope greater than ramp slope.

If the signal slope and ramp slope are equal, b is zero and there is no overshoot or undershoot. Convergence to equilibrium occurs in only one conversion period, as illustrated in Figure 13.

Figure 13.

Conversion cycles with equal signal slope and ramp slope.

The fact that b is zero in this case causes the difference equation be reduced to the simple equation: $v [k] = x [k] = cu [k]$ . This equation is not recursive; thus, the corresponding system function has no poles. It also has no zero because the output v^[k] is dependent only on the present value of the input x^[k]. This property may be verified by considering the pole–zero plot of Figure 7. When b is zero, the pole and zero of the system both lie at the origin, effectively canceling each other. The result is a system function that has no zero and no pole. Under these conditions, the system output is a function only of the present input sample, x^[k] = c. When b is zero, the sequence of converter output peaks converges to c after the first iteration of the difference equation, regardless of past values of the output or input, which indicates that the equilibrium voltage v_e = c in this case.

Conclusion

In this report, design comparison between traditional and proposed charge balance A/D converter is introduced. Then, stable analysis of a proposed charge balance A/D converter is discussed. The stable input limit formula is demonstrated both in time domain and frequency domain. For the traditional charge balance A/D converter, it is stable if and only if the magnitude of the input signal current is less than one half the magnitude of the reference current, and the proposed converter can be stable for load cell’s input signals as large as the reference. On the other hand, since this report limits the analysis on universal model, for which the metrics and parameters are not clarified, the proposed system model will be verified by experimental data in our future work. We believe that the proposed converter can provide better robust and signal-to-noise ratio for high-accuracy load cell signal acquisition.

Footnotes

Handling Editor: Mohamed Elhoseny

Declaration of conflicting interests

The author(s) declared no potential conflicts of interest with respect to the research, authorship, and/or publication of this article.

Funding

The author(s) received no financial support for the research, authorship, and/or publication of this article.

References

Zeng

Oversampling application design based on Σ-Δ ADC. Electron Test 2016; 13(8): 118–119.

Zhang

Hayahara

Hirano

et al . An optimal design consideration for higher-order delta-sigma AD converter. J Circuit Syst Comp 2011; 11(2): 309–312.

Han

Lin

FJ.

A gated ring oscillator based ΔΣ time to digital converter using Tie-skew shaping technique. Microelectronics & Computer 2017; 34(11): 43–47.

Maghari

Moon

UK.

A second-order ΔΣ ADC using noise-shaped two-step integrating quantizer. IEEE J Solid-St Circ 2013; 48(6): 1465–1474.

Yuan

Zhao

Design of a sigma-delta A/D converter for battery measurement chip. Microelectron Comput 2014; 31(11): 143–147.

Amini

Johns

DA.

A flexible charge-balanced ratiometric open-loop readout system for capacitive inertial sensors. IEEE T Circuits-II 2015; 62(4): 317–321.

Yang

Yao

Zeng

et al . Design of self-timed high precision sigma-delta ADC. Acta Sci Nat Univ Nankaien 2016; 49(1): 35–41.

Sanakhan

Mahery

Babaei

et al . Stability analysis of boost dc-dc converter using Z-transform. In: IEEE 5th India international conference on power electronics, Delhi, India, 6–8 December 2012. New York: IEEE.

Bharti

Rai

Gupta

RP.

Modelling and simulation of buck boost DC-DC converter with high stability for low power application. VSRD Int J Electr Electr Commun Eng 2012; 2(9): 679–686.

10.

Chao

Hou

Liu

et al . A single opamp third-order low-distortion delta-sigma modulator with SAR quantizer embedded passive adder. IEICE T Electron 2014; 97(6): 526–537.