Performance Evaluation of Multi-Core Architectures in Training and Simulation: A Case Study with AMD and Intel Dual-Core Systems

Abstract

The defence training and simulation industry is increasingly using server CPUs for processing data. Distributed simulation data creates a large number of small packets that must be processed at the network level before the higher level simulation processing is performed. As network traffic increases it becomes a burden on the server CPUs, which need to process more packets and still have room for application software. Multi-core processor systems are being introduced as a solution to the increase in processor utilization. In this work, we evaluate the performance of servers based on the dual-core AMD Opteron and the dual-core Intel Xeon processors while executing in a typical distributed simulation environment. First, we illustrate the high processing power needed to process a network stream with small packet sizes. Second, we specify the differences between two major competitors in the server chip market, Intel's dual-core Xeon processor and AMD's dual-core Opteron processor. We then test the maximum throughput of servers outfitted with the chips against a baseline dual single-core processor Intel server. The tests use three separate log files to characterize the effect that packet size has on the network throughput. Log files are used to make the test reproducible and are generated from the actual simulation along with the network simulation.

Keywords

Training and simulation performance evaluation multi-core processors distributed interactive simulation computer networks

Get full access to this article

View all access options for this article.

References

1. Zhao, L. , Makineni, S. , Illikkal, R. , Iyer, R. , Bhuyan, L. (2004) Efficient caching techniques for server network acceleration. Proceedings of the Advanced Networking and Communications Hardware Workshop, Munich, Germany, 19-23 June, pp. 2–11.

2. Clark, D.D. , Jacobson, V. , Romkey, J. , Salwen, H. , (1989) An analysis of TCP processing overhead. IEEE Communications, 27, pp. 94–101.

3. Foong, A.P. , Huff, T.R. , Hum, H.H. , Patwardhan, J.R. , Regnier, G.J. (2003) TCP performance re-visited. Proceedings of the IEEE International Symposium on Performance Analysis of Software and Systems, Austin, TX, USA, 6-8 March, pp. 70–79, IEEE, USA.

4. Sarkar, P. , Uttamchandani, S. , Voruganti, K. (2003) Storage over IP: When does hardware support help?. Proceedings of the 2nd USENIX Conference on File and Storage Technologies, San Francisco, CA, USA, 31 March-2 April, pp. 231–244, USENIX Association, Berkeley, CA, USA.

5. IP Storage Working Group (2005) IP Storage Charter.

6. RDMA Consortium (2006) Architectural Specifications for RDMA over TCP/IP.

7. Kant, K. (2003) TCP offload performance for front end servers. Proceeding of the IEEE GlobeCom Conference, San Francisco, CA, USA, 1-5 December, pp. 3242–3247, IEEE, USA.

8. Techworld: The UK's Infrastructure & Network Knowledge Center (2005) To TOE or not to TOE.

9. Senapathi, S. and Hernandez, R. (2004) Introduction to TCP offload engines. Dell Power Solutions, Austin, TX, USA.

10.

10. Adaptec, Inc. (2002) Advantages of a TCP/IP offload ASIC.

11.

11. Makineni S. and Iyer, R. (2003) Measurement-based analysis of TCP/IP processing requirements. Proceedings of the Int'l Conf. on High Performance Computing, Hyderabad, India, 17-20 December.

12.

12. McFarlane, R., (2005) Network Software Architectures for Real-Time Massively-Multiplayer Online Games. MSc Thesis, McGill University, Montreal, Quebec, Canada

13.

13. The Cell Project at IBM Research. (web: http://www.reseqarch.ibm.com/cell/)

14.

14. Intel Corp. (2003) Hyper-Threading Technology. (web: http://www.intel.com/business/bss/products/hyperthreading/overview.htm)

15.

15. 3COM, Inc. (2005) 3Com Gigabit Server NIC, Product Details, (web: http://www.3com.com/products/en\_US/detail.jsp?tab=features\&pathtype=purchase\&sku=3C996B-T)

16.

16. Intel Corp. (2005) Intel Processor Number Details. (web: http://www.intel.com/products/processor\_number/index\_view\_xeon.htm)

17.

17. Advanced Micro Devices, Inc., (2005) AMD Opteron Processor with Direct Connect Architecture.

18.

18. Advanced Micro Devices, Inc., (2003) AMD Opteron Processor for Servers and Workstations Product Information. (web: http://www.amd.com/usen/Processors/ProductInformation/0.30\_118\_8796\_8804,00.html)

19.

19. Lamboray, E., (2004). A Communication Architecture for Telepresence in Virtual Environments. PhD Dissertation, Swiss Federal Institute of Technology, ETH, Zurich, Switzerland.

20.

20. ANSI/IEEE International Standard 1278 (1993) Protocols for Distributed Interactive Simulation. Institute of Electrical and Electronics Engineers, NJ, USA.

21.

21. Hofer, R. , and Loper, M. , (1995) DIS Today. Proceeding of the IEEE, 83, 8, pp. 1124–1137.

22.

22. Hardy, D. em et al}, (2001) Advanced Distributed Simulation: Decade in Review and Future Challenges. Space and Naval Warfare Systems Center Biennial Review, US Navy, San Diego, CA, USA.

23.

23. Dwyer, D , Oser, R. , Salas, E. , and Fowlkes, J. , (1999) Performance Measurement in Distributed Environments: Initial Results and Implications for Training. Military Psychology, 11, 2, pp. 189–215.

24.

24. Kantawala, A. , Parulkar, G. , and DeHart, J. , (1997) Supporting DIS Applications using ATM Multipoint Connection Caching. Proceedings of the INFOCOM, Kobe, Japan, 7-12 April 1997, IEEE, Washington, DC, USA.

25.

25. Close Combat Tactical Trainer, Lockheed Martin, Inc., Orlando, FL, USA.

26.

26. Training Systems and Services, Boeing, Inc., St Louis, MO, USA.

27.

27. Distributed Mission Training, Northrop Grumman, Inc., Orlando, FL, USA.

28.

28. Microsoft Performance Monitoring Tool. (web:http://www.microsoft.com/technet/prodtechnol/windows2000pro/reskit/part6/proch27.mspx)

29.

29. G.M. Amdahl , (1967) Validity of the Single-Processor Approach to Achieving Large-Scale Computing Capabilities. Proc. Am. Federation of Information Processing Societies Conf., AFIPS Press, pp. 483–485.