Abstract
This paper presents an end‐to‐end rate control algorithm for packet switching networks that is executed at the traffic entry nodes. The controller estimates both the bottleneck queue length and available bandwidth to compute the input rate. The aim of the algorithm is to preserve all advantages of the end‐to‐end principle without incurring in reduced performances typical of algorithms that do not use explicit feedback.
The proposed End‐to‐End Rate Control Algorithm (ETERCA) is implemented in the context of ATM networks and compared w.r.t. the Explicit Rate Indication Control Algorithm (ERICA) over single bottleneck scenarios and GFC‐2 test bed. Simulation results clearly indicate that ETERCA ensures network stability, full utilization and fairness in bandwidth allocation also in the presence of networks with large bandwidth‐delay product.