CMOS implementation of a current-mode fully programmable interval type-2 fuzzifier

2.1 T1 fuzzifier

Figure 4 shows the proposed structure for the T1 fuzzifier. It is based on modified Z-shape generator introduced in [13].

Figure 5 shows the effects of control parameters on I_out1, I_out2, and I_out.

The fuzzy-grade interval [0, 1] is represented by [0, I_H]. I_H represents maximum MV in both Z-Shape generators and T1 fuzzifier. I_F1 and I_F2 indicate the falling points and I_S1 and I_S2 indicate the slope values of falling edges (K₁ and K₂) in Z-Shape generators. It is clear that I_F1, I_F2, I_S1, and I_S2 determine the falling point, rising point, slope of falling edge (K₁), and slope of rising edge (K₂) in T1 fuzzifier, respectively.

Figure 6 shows the schematic of modified the Z-Shape generators used in Fig. 4.

The slope (K_i) is determined by Programmable Current Mirror (PCM) circuit. Programmability of the slope values of the PCM is obtained by varying I_S in the predefined intervals.

The proposed PCM circuit is shown in Fig. 7. In Fig. 7(a) the lower NMOS devices provide different ratios of I_in, indicated by the fractions in front of each branch. Upper PMOS devices all have the same size.

Devices M_A-M_H are used to select the copy ratio. These devices are controlled by the control signals V₁-V₈ coming from the control circuit in Fig. 7(b).

The control circuit ensures that at any given moment, only one of the control signals may be high (V_DD), therefore only one copy ratio may be selected. Programmability is achieved by varying a control current, I_S, in an interval from 0.2uA to 1uA. The interval is divided to 0.1uA sections. At each section, one of the control signals V₁-V₈ is high and the rest are zero. Table 1 shows which control signal is active for each interval of I_S.

Figure 8 is presented to elaborate operation principle of the circuit in Fig. 7(b). In Fig. 8(a), let I_S = 0uA. This pushes the PMOS devices into deep triode region and V_X will be close to V_DD. By increasing I_S NMOS devices begin sinking current and pulling V_X lower. When K × I _S increases sufficiently further 1uA, NMOS devices are pushed deep into triode region and V_X will be close to zero. As depicted in Fig. 8(b), decreasing the copy ratio K, increases the value of I_S in which V_X goes from V_DD to GND.

In Fig. 7(b), the copy ratio for each set of M_ai and M_bi is greater than M_a,i +1 and M_b,i +1. This causes V_X,i to switch from V_DD to zero for a smaller I_S than does V_X,i +1. Upper PMOS devices all have the same size.

Figure 9 shows control signals V₁-V₈ and also V_X1-V_X8 versus I_S which supports the data in Table 1.

The circuit in Fig. 7(a) can be modified as in Fig. 10, to reduce the power consumption. In circuit of Fig. 7(a), only one of the branches determines the output current at any given instance, and the power consumed in the rest of the branches is wasted. Transistors M _R1 -M _R8 , as shown in Fig. 10, switch off all branches but the active one, thus reduce the power consumption.

The main advantage of the proposed slope tuning method is that regardless of the number of different slope values, it needs only one bonding pad for PCM to apply I_S. Whereas in [10–12], the number of bonding pads depends on the number of required slopes. Moreover, the method used in [11], employs on-chip resistors for slope value programming that increases the required chip area considerably. Therefore, the proposed PCM is more suitable for general-purpose FLC chips.

The output current of Z-shape MFGs for I_in >  I_Fi can be expressed as follows: I out i = I H - K i × ( I in - I F i )(1)

To obtain a triangular shape in Fig. 5, the following equation must be satisfied I out 2 | I in = I F 1 = 0(2)

Substitution of Equation (2) in Equation (1) results: I F 2 = I F 1 - I H K 2(3)

Also, to obtain a trapezoidal shape, in Fig. 5, the following equation must be satisfied I F 2 = ( I F 1 - Δ I ) - I H K 2(4)

Since UMF and LMF can have different shapes, application of the proposed current-mode IT2 fuzzifier in [10], will be limited to cases where UMF and LMF have the same shapes. Because in [10] I _LMF  = I _UMF -I _SHIFT , where I _SHIFT is used to program width of the FOU. Also the proposed IT2 MFG in [11], is limited to cases where rising and falling slopes in UMF and LMF are the same for a particular IT2MF. To overcome these limitations, the presented structure in Fig. 11 is used. In this structure, shapes of UMF and LMF can be determined independently. Slopes of rising and falling edges, height and width of generated IT2MFs are also independently programmable.

3.1 IT2 MFG circuit

Figure 12 shows simulation results of the T1 fuzzifier circuit. In Fig. 12(a) K₁ = K₂ = 2, I_F2 = 1uA, and I_F1 is varied from 6uA to 15uA in 1uA steps. In Fig. 12(b) K₁ = K₂ = 2, I_F1 = 15uA, and I_F2 is varied from 1uA to 10uA in 1uA steps. In Fig. 12(c) K₂ = 2, I_F1 = 6uA, I_F2 = 1uA, and K₁ varies from 0.5 to 2.25 in 0.25 steps. In Fig. 12(d) K₁ = 2, I_F1 = 20uA, I_F2 = 1uA, and K₂ varies from 0.5 to 2.25 in 0.25 steps.

Figure 13(a) shows several IT2MFs generated by the proposed IT2 fuzzifier that confirm its ability to generate different MFs. Control currents used for generation of these MFs are listed in Table 2. The waveforms in Figs. 19 and 20 are based on Equations (1), (3), and (4). For instance, the circuit operation can be checked by substituting the data corresponding to I_UMF3 and I_LMF4 from Table 2 in Equations (3 and 4), respectively.

Figure 13(b) shows sunk currents from V_DD for IT2-MFs presented in Fig. 13(a). To estimate the power consumption, it is measured for the MFs shown in Fig. 13(a). The average power consumption is approximately 570μW.

3.2 Power supply noise analysis

Circuits are often supplied from noisy lines. For this reason, an 180 mVpp noise is applied to the power supply (V_DD) to show its effect on circuit output. Building blocks of the proposed IT2 fuzzifier are current mirrors. So, the copied current will mostly depend on device ratios. Therefore, ideally the circuit is impervious to supply noise. Figure 14(a) shows the noisy power supply. Figure 14(b) and (c) show the ideal and noisy output currents for IT2 fuzzifier, respectively.

3.3 Mismatch analysis

The stochastic nature of the fabrication process causes mismatch in physical parameters (Na, μ, Tox) and layout dimensions of the MOS transistors which leads to mismatch in their electrical parameters. That is, technological parameters vary around their nominal values, therefore one should accept some degree of tolerance in performance of the circuits.

Devices fabricated in a CMOS process exhibit two components of mismatch: Systematic and Random (stochastic). Non-uniform thermal distribution during the fabrication process, dimensional errors, device orientation, etc, are some possible reasons for systematic mismatch. However, systematic mismatch is deterministic, predictable and can be extensively reduced with proper layout. Random mismatch represents the stochastic and unpredictable portion of mismatch. Statistical variations in the number of dopant atoms and dopant diffusion, edge roughness, polysilicon grain effects, etc, are some possible reasons for random mismatch. Larger device sizes and better process control reduce the random mismatch [1, 14].

In our design, systematic mismatch can be greatly reduced with proper layout and implementing the current mirrors close to each other. Therefore, there remains only the random mismatch [1]. Let the current in an MOS transistor to be: I D = 1 2 β ( V GS - V TH ) 2(5)

Where β = μ n · C OX · W L. It can be shown that [1, 14] σ ( V t ) = A V t WL(6) σ ( β ) = A β WL(7)

Where δ (V _t ) is the standard deviation of the threshold voltage, δ (β) is the standard deviation of the current factor and A _{V t} and A _β are technology dependent parameters. W and L are width and channel length of transistors, respectively. According to the Equations (6 and 7), we can conclude that the random mismatch can be reduced by selecting larger sizes for transistors.

In TSMC 0.18um process, A _{V t}  = 5mV . μm and A _β  = 1.04 % . μm for NMOS devices and A _{V t}  = 5.49mV . μm and A _β  = 0.99 % . μm for PMOS devices [15]. Monte Carlo analysis has been used to investigate effects of the random mismatch on the circuit performance. Since the statistical significance of 30 iterations is quite high, therefore a 30 points Monte Carlo analysis is done. If the circuit operates correctly for all 30 iterations, there will be a 99% probability that over 80% of all possible component values operate correctly [16]. Figure 15 shows mismatch simulation result of the IT2-fuzzifier.

The proposed PCM circuit has very low sensitivity to mismatch. This accounts for an advantage in comparison to other methods that employ resistive arrays for slope programmability in which resistors are prone to 20 to 30% tolerance. Also the proposed PCM circuit has very low sensitivity to mismatch. This is because the slope only depends on I_S. The slope is constant when I_S is within the intervals defined in Table 1. Therefore setting I_S to be equal to the average value of each interval ensures a very low sensitivity to mismatch. There might be still a small sensitivity to mismatch present, which is due to the circuit in Fig. 10 which can be further reduced by selecting larger device sizes at the cost of larger chip area.

In this subsection the effect of temperature variation on performance of the circuits is discussed. Since the threshold voltage of transistors exhibit a temperature coefficient of approximately −1 mV/°K [14], it yields a −60 mv change across temperature range (270 to 330°K). Figure 16 shows the effect of temperature variation on performance of the IT2 fuzzifier.

3.5 Process corner analysis

Figure 17 shows output of the IT2 MFG in TT, FF, FS, SF, and SS process corners. T stands for ‘typical’, F for ‘fast’, and S for ‘slow’. The first letter refers to NMOS devices and the second to PMOS. In a ‘fast’ corner the threshold voltage drops below the normal value. The opposite happens in a ‘slow’ corner. The circuit operates in current-mode and by a first-order approximation, the current copied by a current-mirror depends only on transistor widths. Therefore, ideally, the output current is not affected by process corner variations. However, in reality, the copied current depends on V_DS too which varies with process corners. This causes some slight changes in I_OUT at different process corners which is shown in Fig. 17.

3.6 Device sizes

NMOS and PMOS device sizes in Figs. 4 and 6 are ( W / L ) N = 10 μ m 1 μ m and ( W / L ) P = 10 μ m 1 μ m, respectively. In Fig. 7(b), all of cascoded PMOS devices have the same size and are equal to ( W / L ) = 10 μ m 1 μ m. Also, size of cascade devices that sink current from I_S, is ( W / L ) = 5 μ m 1 μ m. Sizes of the labeled NMOS devices in Fig. 7(b), are listed in Table 3.

In Fig. 10, devices M_A-M_H and M_R1-M_R8 all have the same size, which is ( W / L ) = 5 μ m 0.18 μ m. Also, all of cascoded PMOS devices have the same size and are equal to ( W / L ) = 20 μ m 1 μ m. Sizes of the labeled NMOS devices in Fig. 10, are listed in Table 4.

3.7 Layout and post layout simulation

Figure 18 shows layout of the IT2-fuzzifier which has an area of approximately 18300μm². Also, Fig. 19 shows layout of the proposed PCM. The proposed PCM occupies 3880μm². The IT2-fuzzifier has 4 PCM blocks which occupy approximately 85% of the total die area. The proposed IT2 fuzzifier can generate 8 different slopes for rising and falling edges of the UMF and LMF, while all slopes are totally independent of each other. However, it only needs 4 pins to inject the currents for controlling the slopes, and any number of slopes can be increased without any need to increase the number of pins.

Figure 20 shows post layout simulation of the proposed IT2 fuzzifier. Table 5 lists the parameters used for post layout simulation.