Optimization of on-chip spiral inductors using coupled NN and TLBO algorithms for low-loss lumped-element CMOS power dividers

Abstract

An efficient layout-level optimization technique based on NN+TLBO algorithm is presented to maximize the quality factor of on-chip spiral inductors at a given frequency. A multi-layer artificial neural network (ANN) is developed to model the on-chip inductors. TLBO algorithm is used in order to optimize the layout space for the on-chip spiral inductors considering constraints of design specifications and desired accuracy level. A four-way K-band lumped-element power divider (PD) is designed in 0.18μm CMOS technology to validate the characterized spiral inductor. The PD achieves an insertion loss less than 2.1 dB, an input return loss better than 10 dB, an output return loss less than 12 dB, and a port-to-port isolation higher than 14 dB from 18 to 26 GHz (K-Band). The chip area is about 0.415 mm² including bonding pads.

Keywords

Spiral inductor optimization neural network TLBO algorithm power divider lumped-element

1 Introduction

On-chip Spiral inductors are essential passive components in silicon-based radio frequency integrated circuits (RFICs) such as voltage controlled oscillators (VCOs), low noise amplifiers (LNAs), power amplifiers (PAs), and lumped-elements power dividers (PDs). Among RF silicon-based technologies, CMOS technology is an attractive choice due to very interesting benefits such as easy scaling, ability to integrate the digital backbone with the analog RF sections, low cost, and low power consumptions [1, 2]. However, High quality factor (High-Q) passive devices are required to obtain excellent circuit operation in a CMOS RFIC process. Therefore, inductor designers need a fast method to choose the desired layout with optimized electrical attributes such as quality factor (Q), inductance (L), and self-resonant frequency (SRF) for a given circuit application.

There are several conventional techniques for modeling the spiral inductors on silicon substrate such as numerical, analytical and empirical approaches [3, 4]. Numerical methods are efficiently accurate but very time-consuming while the analytical and empirical methods are time efficient but are not accurate enough. In general, it can be said that the conventional methods are inefficient for optimizing performance and studying tradeoffs [5].

In this paper, an efficient procedure is used to synthesis the layout space of the on-chip spiral inductors. A multi-layer artificial neural network is applied to model the on-chip spiral inductors based on its geometrics and electrical specifications. It allows more freedom for tradeoff analysis between contending objectives such as quality factor (Q), area, and SRF for on-chip inductors. In addition, Teaching–learning-based optimization (TLBO) algorithm [6] is used to explore the best layout space that maximizes the quality factor based on the limitations applied by design specifications.

Power dividers (PDs) and power combiners are widely used in microwave and millimeter-wave circuits such as balanced power amplifiers, mixers and phase shifters. One of the most commonly used power dividers is Wilkinson PD [7]. The Wilkinson PD has simple structure and is conventionally implemented using transmission lines. A conventional two-way Wilkinson PD is shown in Fig. 1. It consists of two λ/4 transmission lines at the center frequency f₀ with characteristic impedance $\sqrt{2 Z_{0}}$ and a high isolation 2Z₀ lumped resistor connected between the output ports. However, the transmission lines consume too much chip area in an RFIC process. Some efforts have been made in the literature to reduce the size of the PD circuits. In [8] an improved lumped-distributed technique is proposed to reduce the circuit area, but the problem of applying transmission lines has still remained. Replacing the transmission line sections with the passive lumped-elements is investigated in [9 –13]. Four-way and two-way 24 GHz miniaturized Wilkinson PDs in standard CMOS technology are presented in [9]. In [12] an extremely miniaturized Wilkinson PD based on a two-step synthesis approach is proposed. A Q-band eight-way lumped PD is designed and presented in [13]. A main drawback is high insertion loss due to substrate losses in standard CMOS process. To overcome this problem, active inductors are applied in [10]. However, in addition to potential linearity problem [9], the active inductors are power-consuming circuits [11].

A K-band four-way lumped-element CMOS power divider is also proposed in this paper to further validate the optimized inductors based on NN+TLBO algorithm. A standard 0.18μm CMOS is applied for circuit implementation at 24 GHz center frequency. The results show that by using the optimized high-Q spiral inductors, the proposed power divider achieves a low insertion loss.

2 Optimized on-chip spiral inductor

The aim of the on-chip inductor optimization is determining a layout geometric dimension with maximum quality factor considering electrical characteristics and predefined specifications [14]. A multi-layer perceptron-based (MLP) neural network is applied to provide a mathematic model for inductors. The trained function obtained by neural network is used in TLBO algorithm for optimization.

2.1 Neural Network (NN) model

Figure 2 shows the MLP neural network which is used in this paper. It consists of an input layer, a hidden layer, and an output layer. In this figure, N is the number of hidden layer neurons and equal to 12 and u and w are the coefficients of the hidden and output layer, respectively. We consider 4 inputs and 3 outputs for NN as shown in Table 1. The processing elements (neurons) of two adjacent layers are connected by weighted edges. Log-sigmoid (Logsig) function is used as activation function for both hidden and output layers.

An accurate EM simulator is used to generate training and testing data sets. For this purpose, 200 different planar hexagonal spiral inductors are simulated in 0.18μm CMOS technology. Out of the 200 simulated spiral inductor, 160 are used for the training and the remaining 40 are used for testing the neural network. Table 2 demonstrates the range of the input parameters. This range is selected based on the foundry SPICE model for spiral inductors. The electrical attributes of the inductors include self-resonance frequency (SRF), inductance (L), and quality factor (Q) are chosen as NN output neurons. Assuming Z11 is the input impedance of the two port Z-parameters, the SRF is measured at the impedance transition frequency and the inductance and quality factor are extracted from EM simulator as $L = \frac{Imag {z 11}}{{2 π f}}$ (1) $Q = \frac{Imag {z 11}}{Real {z 11}}$ (2)

All of the inputs and outputs are normalized to put in the range of [0, 1]. The training step is used to adjust weight and bias values of the proposed NN. The training error is set to 0.002 in this work. Finally, achieved training function is tested by the last 40 considered data and the obtained outputs of the function are unnormalized and compared with basic outputs. The training function is suitable for TLBO algorithm if the average error percent is low.

To verify the NN model accuracy (how close the NN outputs to the EM simulated values), we used average relative error as a statistical measure. For each output parameter, the average relative error between the NN model outputs and corresponding target can be calculated as $ɛ_{r e l a t i v e} = \frac{\sum_{n}^{1} (x - y)}{n y}$ (3)

Here, n is the number of data-set samples, x is the output of the NN model, and y is the EM simulated value. Table 3 shows the NN model accuracy at 18 and 24 GHz frequencies. The average relative error of less than 3% for L, Q, and SRF demonstrates that the trained NN has excellent accuracy.

2.2 Teaching–learning-based optimization

Teaching-Learning-Based algorithm (TLBO) is a novel population-based optimization method presented by Rao et al. [6] based on the influence of a teacher on knowledge of the students in a classroom. A group of learners are considered as population. The different lessons are considered as the design variables that should be optimized. A specific fitness function evaluates the knowledge of the learners. The teacher is a person with the best output of the fitness function who shares his/her knowledge with other learners. The knowledge of the learners directly depends on the quality of the teacher. Two different phases including teacher and student phase are implemented in TLBO to increase the knowledge of the class.

During the teacher phase, the teacher tries to shift the mean value of individuals (X_mean) towards a new mean (X_teacher). The knowledge of each student is modified by teacher as $X_{new} = X_{old} + r . (X_{teacher} - T_{F} X_{mean})$ (4)

Where, r is a random number generated in the range of 0 to 1. T_F is the teaching factor and randomly determined equal to 1 or 2. A modified student X_new replaces X_old if it is found to be better than X_old.

In the student phase, the knowledge of students is raised through interactions among themselves. For this purpose, two students X_i and X_j (i ≠ j) are randomly selected to interact according to the following mathematical expressions $X_{new} = X_{old} + r . (X_{i} - X_{j}); if X_{i} > X_{j}$ (5) $X_{new} = X_{old} + r . (X_{j} - X_{i}); if X_{j} > X_{i}$ (6)

Again X_new is accepted only if it is better than X_old. Table 4 shows the pseudo code for TLBO algorithm.

Simplicity in implementation and low dependency of the final solution convergence to the initial population are two main advantages of the TLBO algorithm. In addition, TLBO requires fewer control variables in comparison with other nature-inspired optimization algorithms like genetic algorithm (GA) and particle swarm optimization (PSO) algorithm [15]. For more details of TLBO algorithm the readers may refer to references [6 , 16].

2.3 NN+TLBO

As mentioned in pervious section, the NN modeling is coupled with TLBO optimization to design and synthesis the spiral inductors. The proposed method combines the advantages of neural network for modeling and TLBO algorithm for optimization. Figure 3 shows the simplified flowchart of the optimization process.

Due to random initialization of individuals in class, multiple solutions of geometries are provided by TLBO algorithm for a given inductance with different values of Q and SRF. From all synthesized inductor geometries, an inductor that has the maximum Q and meets the design specifications of SRF, area, and L is selected by TLBO algorithm as optimized design. The optimization function for a given L can be mathematically formulated as $\begin{matrix} Maximize Q_{| L_{given}} \\ Subject to N_{min} \leq N \leq N_{max} \\ W_{min} \leq W \leq W_{max} \\ d_{min} \leq d \leq d_{max} \\ s_{min} \leq s \leq s_{max} \\ SRF > {SRF}_{given} \end{matrix}$

Here, SRF_given is the minimum SRF required for the inductor in the design and N_min, N_max, W_min, W_max, d_min, d_max, s_min, and s_max are minimum and maximum bounds of corresponding optimization variables.

The TLBO-search process is terminated if the maximum generation number is achieved. In this paper, the maximum number of generation is taken to be 500.

3 Power divider design

A lumped-element based PD is obtained by replacing the transmission line sections by their equivalent lumped LC π-network or T-network [17]. Compared to a LC T-network, less number of high-loss high-cost inductors is used in a LC π-network. For a distributed transmission line with characteristic impedance Z₀ and electrical length βl, the ideal lumped components of equivalent LC π-network are derived by equating the ABCD matrices of the transmission line and the lumped LC network as below $[\begin{matrix} cos β l & {jZ}_{0} sin β l \\ {jY}_{0} sin β l & cos β l \end{matrix}] = [\begin{matrix} 1 + \frac{Y_{2}}{Y_{3}} & \frac{1}{Y_{3}} \\ Y_{1} + Y_{2} + \frac{Y_{1} Y_{2}}{Y_{3}} & 1 + \frac{Y_{1}}{Y_{3}} \end{matrix}]$ (7) where β = 2π/λ is wave number. By replacing Y₁ = Y₂ = jωC, Y₃ = 1/jωL in the above equation, the values of L and C are calculated as $L = \frac{z_{0}}{ω}$ (8) $C = \frac{1}{z_{0} ω}$ (9)

It should be noted that the values of L and C in Equations (8) and (9) are calculated considering that these components are ideal and independent. In the reality the impact of parasitic elements of the passive components must be considered. The Input and the output ports are matched to 50Ω impedances.

The schematic of the proposed four-way lumped-element PD is shown in Fig. 4. Two two-way dividers are connected in cascade with another two-way divider (binary-tree manner) to form a four-way power divider. As shown in this figure, the transmission lines are replaced by lumped LC π-networks. Considering the impact of parasitics, the final component values of the inductors, capacitors, and resistors are also shown in a table in Fig. 4.

All inductors used in this work are designed and optimized through full wave electromagnetic (EM)simulation. Topmost metal layer with the thickness of 2.5μm is used to reduce the ohmic loss of the inductors. Since a pattern grounded shield can reduce the self-resonance frequency (SRF) of inductors due to increased capacitance to ground [18], this technique is not used in this work.

4 Results and discussions

4.1 Optimization algorithm for spiral inductor design

With the aim of finding an inductor structure for a target-inductance with an acceptable accuracy level, NN+TLBO based optimization is used. Table 5 shows the optimized layout geometries (rounded values) for the maximum Q and desired inductance value of 296pH at 24 GHz operating frequency. These layout geometries are selected from a set of 15 different synthesized inductors that meet the design specifications within ±5nH accuracy. To validate the accuracy of the proposed method, the optimized layout is also simulated using EM simulator. As shown in Table 5, the optimized spiral inductors confirm perfect matching with EM simulation results.

To evaluate the speed of the proposed algorithm, both proposed algorithm and EM simulation are run on a 3.3 GHz Intel(R)-i3 machine with 4 GB RAM. To finding a target inductance of 296pH at 24 GHz operating frequency, the proposed approach is run for 20 times and the average run-time is about 12.5 seconds. It is an interesting result in comparison with 1050 seconds the run-time of each EM simulation.

4.2 Four-way Wilkinson PD

The proposed Wilkinson PD is designed with a standard 1P6M 0.18μm bulk CMOS technology. Figure 5 shows the chip layout of the proposed PD. The chip size is about 0.415 mm² including bonding pads. Layout is an important issue for the overall performance of the circuits operating at high frequencies. We used Metal 6 (topmost metal) for all RF signal lines to have a low loss and low substrate coupling. To ensure minimum degradation and reflection of the RF signal, the length of RF paths are considered as small as possible with 45° angle at the turning points. Metal-insulator-metal (MIM) capacitors and poly-silicon resistors are used for shunt elements and isolation resistors, respectively. The spiral inductor layouts are optimized using the proposed NN+TLBO algorithm which is described in detail in the previous sections.

Over the Operating frequency range from 18 to 26 GHz (K-band), the per-layout simulation exhibits an insertion loss of less than 0.8 dB and post-layout simulation results an insertion loss less than 2.1 dB as shown in Fig. 6. The port-to-port isolation (S23) of higher than 15 dB for pre-layout and better than 13 dB for post-layout simulation is also shown in Fig. 6. According to this figure, the simulated post-layout isolation is about 18 dB at 24 GHz center frequency.

The pre- and post-layout simulation results for input/output return loss of the proposed power divider versus frequency are shown in Fig. 7. The input return loss (S11) is better than 15 dB for pre-layout simulation while it is less than 10 dB for post-layout simulation. Output return loss (S22) is less than 25 dB in pre-layout simulation while post-layout simulation results S22 of better than 12 dB. Therefore, the proposed PD maintains a good input/output match to 50Ω across the frequency band.

The performance of this four-way power divider is summarized and compared with previously reported two-way and four-way CMOS Wilkinson PDs in Table 6. It shows that the proposed four-way PD exhibits better insertion loss than four-way PD reported in reference [9] and two-way PD proposed in reference [19]. In addition, if the two-way PD in [9] is used in a binary-tree manner to form a four-way PD, it can be estimated that the overall insertion loss will be more than 2.8. Therefore, the proposed PD achieves better insertion loss in comparison with prior publications. In addition, it shows a suitable port-to-port isolation and reasonable input/output impedance matching.

5 Conclusions

An efficient layout synthesis method based on NN+TLABO algorithm is presented for CMOS on-chip spiral inductors. A 3-layer perceptron neural network has been developed to efficiently model the RF on-chip spiral inductors with less than 3% accuracy respect to data generated by EM simulator. The layout space optimization of on-chip spiral inductors is done with TLBO algorithm. A K-Band low-loss lumped-element power divider has been also designed and simulated in a standard 0.18μm CMOS technology. Comparing with previously reported works, the proposed design shows better performance in insertion loss. In addition, it shows good input/output impedance matching and suitable port-to-port isolation. The chip area of the design is 0.415 mm² in 0.18μm CMOS technology.

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