Hardware efficient circuit for low error logarithmic converter

Abstract

The need to implement high-speed Signal processing applications in which multiplication and division play a vital role made logarithmic arithmetic a prominent contender over the traditional arithmetic operations in recent years. But the logarithm and antilogarithm converters are the bottlenecks. In order to reduce the logarithmic conversion complexity, several works have been introduced from time to time for correcting the error in Mitchell’s algorithm but at the cost of hardware. In this work, we propose a 32-bit binary to the binary logarithmic converter with a simple correction circuit compared with existing techniques. Unlike the current methods that use the linear piece-wise approximation in the mantissa, we propose a weighted average method to correct the error in Mitchell’s approximation. The maximum error percentage from the proposed work is 0.91%, which is 16.9% of Mitchell’s error percentage.

Keywords

Logarithmic arithmetic logarithmic number system logarithmic conversion Mitchells algorithm error correction DSP systems

1. Introduction

In many applications like radio communications, audio, video, aircraft, and in a large number of compact mobile consumer goods, digital signal processing (DSP) thus becomes pervasive. With the growing demand for DSP, there has been a rising need for hardware distribution of binary multipliers and binary dividers that are quicker and more productive in the area. The use of logarithms simplifies the arithmetic computations in both binary and decimal, as in [1]. Logarithms were used to simplify multiplication, division, and powering operations to the stage of addition and subtraction, where powering operations are simplified to multiplication [2].

The exact method for calculating the logarithm involves storing the logarithmic tables in memory, and such approaches are highly-priced for speed and hardware. For a few applications like image processing and DSP applications, a trade-off can be rendered by raising the conversion’s precision to reduce the system’s delay and power consumption. To simplify the logarithm computations, [3] proposed an algorithm for calculating the estimated log2 of a binary word. Here, the author used a straight-line approximation of the logarithm function for intervals between the two potential powers. The logarithmic values of real and Mitchell are shown in Fig. 1. Mitchell’s algorithm is less complicated than the traditional method of storing logarithmic tables but at the inevitable inaccuracy cost. Several approaches have been proposed to decrease the inaccuracy in Mitchell’s algorithm. [4] algorithm divides the two potential powers into four intervals. Here the authors performed straight-line approximation in each interval. The coefficients of every line were chosen by the trial and error method. This method is used to minimize the inaccuracy in the subsequent approximation of the logarithm [5]. Often they used four sub-intervals and chose appropriate straight-line estimation to reduce the average error. These two methods are more successful approaches and also challenging to implement. [6] has used two straight-line approximations with less complexity, but the accuracy achieved by the error correction is not sufficient. To reduce errors, [7] has used two, three, and six subintervals. These methods are effective with an increase in the number of subintervals, which leads to an increase in effective area.

Figure 1.

LOGN curve of real and Mitchell approximation.

Mahalingam and Ranganathan [8] proposed an upgrade to Mitchell’s multiplier by an operand division method. The proposed architecture enhances the effectiveness of Mitchell’s multiplier by 44.7 percent. However, logic gates become doubles. Gandhi et al. [9] used estimated lead-one detectors to minimize the Mitchell multiplier area and power consumption. Using approximate lead-one detectors, the authors decreased Mitchell’s power consumption by 55%. However, there is a massive error in the multiplication of small numbers.

Kim et al. [10] have used bit truncation to make Mitchell’s multiplier design more potent. Authors reduce the logarithmic representation of multiplier inputs to use smaller barrel shifters. The proposed truncation greatly decreases the delay, power, and area compared to the original Mitchell multiplier, but at a higher error rate. Kim et al. [11] successfully solved the truncated Mitchell multiplier’s high error problem by adding an iterative truncated Mitchell multiplier. The iterative approach greatly increases precision at the expense of higher power consumption.

For the addition of the mantissa, which includes a small barrel shifter configuration, Liu et al. [12] use approximate truncated adders. Their multiplier has the same accuracy as the multiplier from Mitchell, offering at the same rate a lower power-delay device.

The iterative logarithm multiplier (ILM) was developed by Babic et al. [13] to improve the Mitchell multiplier’s accuracy. To improve the Mitchell multiplier’s accuracy, the iterative logarithm multiplier (ILM) [13] was developed by Babic et al. ILM is an inexpensive and easy multiplier that achieves arbitrary precision by an iterative process. ILM uses a simpler approximation of the product, unlike Mitchell’s multiplier. Simple ILM has a relatively high mean relative error of about 10% due to the product’s generalized approximation. The accuracy of the multiplier increases as the mechanism is iteratively implemented. The ILM design generates a relative mean error of around 1 percent with just one iteration for error correction. The desirable feature of ILM is the ability to perform each iteration simultaneously. This role made the ILM extremely useful in neural networks [14].

By constructing a truncated iterative multiplier (TIM), Ahmed and Srinivas [15] discussed the problem of sophistication in ILM. TIM supports the product approximation approach to ILM, but TIM truncates the product approximation terms to allow smaller adders and shifters, unlike ILM. Truncation succeeds in a major reduction in the chip region than ILM, but it doesn’t provide a latency change. TIM produces a smaller error compared to ILM from an accuracy point of view.

In the works described above, there is adequate research on logarithmic multipliers. In these works, all authors aim to change the Mitchell logarithmic multiplier architecture and have tried to reduce the error but failed to minimize the errors due to logarithmic and antilogarithmic converters. Therefore, modifying the logarithmic and antilogarithmic converters is the most suitable approach to reducing conversion errors, and these corrections are reflected in all arithmetic operations. Hence, in the present paper, we have proposed logarithmic converters with less complexity and less area.

In this work, a novel approach to design a 32bit binary to binary logarithmic conversion based on weighted average correction of Mitchell’s algorithm for low power applications is proposed. The main contributions to this paper can be summarized as follows:

This paper presents a new error-correcting circuit to improve Mitchell’s algorithm’s accuracy based on the method of weighted average.

The Error-correcting circuit corrects the mantissa term based on the characteristic part of the logarithmic conversion.

Unlike the existing methods, the proposed error correcting circuit will remain simple irrespective of the number of bits used for correction in the mantissa.

Next, the paper shows that the proposed logarithmic conversion provides better offsets than conventional precise scaling methods.

This paper has the following texture: The related work is discussed in Section 2. The logarithmic converter (LC) is summarised in Section 3. Section 4 elaborates on the proposed work. Section 5 contains the experimental results with error and hardware analysis. Finally, Section 6 brings the paper to a close.

2. Related work

The logarithmic conversion method is of two types:

Techniques using the lookup tables and interpolation.

Methods that are based on the Mitchell algorithm, which calculates the logarithms by shifting and counting operations.

Although memory is used in lookup table-based approaches, Mitchell’s algorithm works without memory but with a loss in accuracy. As a result, several scholars have offered ways to increase Mitchell’s algorithm’s accuracy. The taxonomy diagram, as shown in Fig. 2, lists the numerous related works in logarithmic conversion. In the following section, we’ll go through some of these ways in more detail.

Figure 2.

Taxonomy of related work.

2.1 Logarithmic conversion using LUT’s

The conventional logarithmic conversion solution uses entire logarithm value tables retained in memory, which is unreliable in processing specifications. Consequently, some researchers discussed the possibility of utilizing smaller lookup tables and use interpolation methods to compensate [16, 17, 18, 19, 20]. The purpose was to determine LUT sizes, which correspond to different logarithmic accuracy levels and trading on precision versus overhead muscle. Attempts to minimize the volume of memory to store lookup tables have a keen interest in Mitchell’s algorithm, terminating the need for lookup tables completely.

2.2 Base two logarithm of binary number using Mitchell’s algorithm

In [3] base two logarithm of binary number is as follows: Let us consider a binary number $N$ in the range $2^{j}\leqslant 2^{k+1}$ where $j=$ 0, $\pm$ 1, $\pm$ 2, $\pm$ 3, …; $k=$ 0, $\pm$ 1, $\pm$ 2, $\pm$ 3, …and $k\geqslant j$ ; $N=b_{k}\ldots b_{3}b_{2}b_{1}b_{0}.b_{-1}b_{12}b_{-3}\ldots b_{j}$ . Here, $N$ can be interpreted as,

$\displaystyle N=\sum_{i=j}^{k}2^{i}.b_{i}$ (1)

Where, $b_{i}=$ 0 or 1 and $b_{k}$ is the Most Significant Bit (MSB) and may assume $b_{k}=$ 1. Now, $N$ can be written as,

$\displaystyle N=2^{k}\sum_{i=j}^{k-1}2^{i}.b_{i}$ (2)

If $2^{k}$ is factored out,

$\displaystyle N=2^{k}\left(1+\sum_{i=j}^{k-1}2^{i-k}.b_{i}\right)$ (3)

Let the term,

$\displaystyle\sum_{i=j}^{k-1}2^{i-k}.b_{i}=f$ (4)

As, $k\geqslant j$ , $f$ would be in the range [0, 1]. Then

$\displaystyle N=2^{k}(1+f)$ (5)

By applying logarithm on both sides,

$\displaystyle\log_{2}N=k+\log_{2}(1+f)$ (6)

Table 1

Comparison of base two binary logarithms of exact and Mitchell algorithm

$N$ decimal	$N$ binary	$\text{Log}_{2}(N)$ exact	$\text{Log}_{2}(N)^{\|}$ Mitchell approx	$\text{Log}_{2}(N)^{\|}$ Mitchell approx
1	00001	0.00000	000.0000	0.00000
2	00010	1.00000	001.0000	1.00000
3	00011	1.58496	001.1000	1.50000
4	00100	2.00000	010.0000	2.00000
5	00101	2.32193	010.0100	2.25000
6	00110	2.58496	010.1000	2.50000
7	00111	2.80373	010.1100	2.75000
8	01000	3.00000	011.0000	3.00000
9	01001	3.16992	011.0010	3.12500
10	01010	3.32193	011.0100	3.25000
11	01011	3.45942	011.0110	3.37500
12	01100	3.58496	011.1000	3.50000
13	01101	3.70043	011.1010	3.62500
14	01110	3.80735	011.1100	3.75000
15	01111	3.90689	011.1110	3.87500

Here, the term $f$ is the fractional part of the binary number that consists of all the bits right of most significant one. By approximating $\log_{2}(1+f)$ by a straight line connecting between successive powers of two points, Mitchell has approximated the actual $\log_{2}(N)$ as $(\log_{2}(N))^{|}$ as in Table 1. To reduce the complexity of calculation, Mitchell has used $\alpha=$ 1 and $\beta=$ 0 in the linear piecewise equation $\alpha*f+\beta$ . Then Eq. (6) becomes as follows,

$\displaystyle(\log_{2}(N))^{|}=k+f$ (7)

The error in the approximation is equals to actual logarithm minus approximate logarithm. Therefore,

$\displaystyle\textit{error}=\log_{2}(N)-(\log_{2}(N))^{|}=\log_{2}(1+f)-f$ (8)

For example, Let $N=$ 219 $=$ (11011011) ${}_{2}$ ; Here $k=$ 7 which represents the most significant one position in $N$ . Because $k$ is a logarithm characteristic and the mantissa is made up of all the bits from the least significant to the most significant, $f=$ 0.1011011. We can reflect $N$ as in Eq. (5), $N=$ 27 (1 $+$ 0.1011011). Using Eq. (7) we get $(\log_{2}(N))^{|}=$ (111.1011011) ${}_{2}$ which equals to (7.7109375) ${}_{10}$ , where the original value is (7.77478706) ${}_{10}$ . It can be observed that it is easy to perform the logarithmic conversion using Mitchell’s algorithm, requiring only shift and count operations.

In [3] suggests that the calculation error is because of a mantissa. Here the error will be in the interval [0, 0.08639]. It can be observed that the error percentage is always positive and is in the range of 0 to 5.3605%. Many research have attempted to reduce this error percentage by using a single estimate in different ranges or applying a counterbalanced component to Mitchell’s output.

2.3 Divided approximation correction

2.3.1 Combet et al. correction

In [4], the interval [0, 1] of mantissa $f$ was divided into four parts, and each part has an independent correction term. The correction term for each subinterval was defined by using the trial and error method. In [4], Combet et al. established a series of coefficients by modifying the equations to reduce the error, which, in effect, greatly enhanced the outcome. The coefficients were deliberately chosen to be fractions of integer numerators and the denominators being two-value powers. The correction equations of the Combet et al. method for the four regions are given below.

$\displaystyle(\log_{2}(1+f)^{|}=f+(5/16)f\hskip 14.226378pt\textit{for}\hskip 1% 4.226378pt0\leqslant f<0.25$ (9) $\displaystyle(\log_{2}(1+f)^{|}=f+(5/64)f\hskip 14.226378pt\textit{for}\hskip 1% 4.226378pt0.25\leqslant f<0.5$ (10) $\displaystyle(\log_{2}(1+f)^{|}=f+(1/8)f\hskip 14.226378pt\textit{for}\hskip 1% 4.226378pt0.5\leqslant f<0.75$ (11) $\displaystyle(\log_{2}(1+f)^{|}=f+(1/4)f\hskip 14.226378pt\textit{for}\hskip 1% 4.226378pt0.75\leqslant f<1$ (12)

The Combets et al. method lowered the average error percentage of the logarithmic conversion from 5.36% in the Mitchell method to 0.451%. However, the technique used by Combet et al. has a significant problem with the large overhead hardware. Another significant problem with this method is that the coefficients are not two potential powers.

2.3.2 Hall et al. correction

In [5] has divided the mantissa m into four regions, each region has a separate correction coefficient. In [5], Hall introduced a set of correction parameters intending to reduce mean square error. The correction parameters of Hall’s method for four sub-regions are given below.

$\displaystyle(\log_{2}(1+f)^{|}=f+(37/128)f+1/128\hskip 14.226378pt\textit{for% }\hskip 14.226378pt0\leqslant f<0.25$ (13) $\displaystyle(\log_{2}(1+f)^{|}=f+(3/64)f+1/16\hskip 14.226378pt\textit{for}% \hskip 14.226378pt0.25\leqslant f<0.5$ (14) $\displaystyle(\log_{2}(1+f)^{|}=f+(7/64)f^{|}+1/32\hskip 14.226378pt\textit{% for}\hskip 14.226378pt0.5\leqslant f<0.75$ (15) $\displaystyle(\log_{2}(1+f)^{|}=f+(29/128)f^{|}\hskip 14.226378pt\textit{for}% \hskip 14.226378pt0.75\leqslant f<1$ (16)

Where $f^{|}=1-f$ , The Hall et al. method minimized the average error percentage of the logarithmic conversion from 5.36% in the Mitchell logarithmic conversion method to 0.845%. However, Hall et al. approach have high hardware consumption since it requires all the mantissa bits. Another significant problem with this method is that the coefficients are not two potential powers.

2.3.3 Abed et al. correction

[7] constructed correction coefficients, which require small and fast circuitry while maintaining accuracy near the method used by Hall et al. Three specific correction approaches were suggested with varying hardware sophistication and precision, focused on equations for two, three, and six regions. The complexity of the circuit increases with an increase in the number of sub-regions. The modified parameters use the mantissa’s first three significant bits. Also, the coefficients are limited to the two powers. The equations of the Abed’s et al. algorithm corrected by 2-region is as follows:

$\displaystyle(\log_{2}(1+f)^{|}=f+(1/4)f_{\textit{3MSB's}}\hskip 14.226378pt% \textit{for}\hskip 14.226378pt0\leqslant f<0.5$ (17) $\displaystyle(\log_{2}(1+f)^{|}=f+(1/4)f^{|}_{\textit{3MSB's}}\hskip 14.226378% pt\textit{for}\hskip 14.226378pt0.5\leqslant f<1$ (18)

Where, $f^{|}_{\textit{3MSB's}}=(1-f_{\textit{3MSB's}}-2^{-3})$ . This method minimizes the average error percentage of the logarithmic conversion from 5.36% in the Mitchell method to 1.5%.

3. Logarithmic converter

The complete implementation of 32-bit binary to binary logarithmic conversion implemented using Mitchell’s algorithm along with the error-correcting circuit is presented in Fig. 3. Here, the logarithmic converter (LC) uses a leading one detector (LOD) circuit, a logarithmic shifter, 32 $\times$ 5 bit ROM, and an error-correcting circuit. The 32-bit output of the LOD circuit is given as the input to the 32 $\times$ 5 ROM. The MOS ROM produces output with size 5-bit depending on the active-high data with the most significant one location. The 5-bit output of the ROM is the characteristic of the logarithm. A logarithmic shifter is used for shifting the input word. After shifting, the mantissa is produced by the logarithmic shifter. The most significant 27bits of the mantissa are considered and are mounted to the right side of the 5bit characteristic to generate a 32-bit logarithmic number. This result represents Mitchell’s value and its corresponding equations from Section 2.2.

Figure 3.

Existing 32 bit binary to binary logarithmic conversion.

3.1 32 bit lead one detector

The 32-bit input word is given to the LOD circuit and a decoded active-high 32-bit output is generated [7, 21, 22, 23]. The 32 Bit Lead One Detector (LOD) identifies the most significant one in the given input. The LOD circuit sets the most significant one position as active high bit and other bit positions to zero. For example, N $=$ 219 $=$ (11011011) 2; k $=$ 7, which represents the most significant one position in N. Since, k $=$ 7 the LOD circuit sets the 8th bit as 1 and remaining bits to zero, hence the output of the LOD is “00000000000000000000000010000000”.

3.2 32 $\times$ 5 bit ROM

The 32 $\times$ 5-bit ROM is utilized to produce binary log2 of 32-bit word equivalent with the most significant one location in each binary 32-bit data. Here, the LOD circuit has output with 32 bits linked to 32 lines of words of ROM and generates the 5-bit binary output. The ROM generates all feasible integer bits of binary to binary logarithms and regulates binary numbers from “00000” to “11111”. In the above example, N $=$ 219 $=$ (11011011) ${}_{2}$ ; here, the output of the LOD circuit is “00000000000000000000000010000000,” and it is given as the input for the 32 $\times$ 5 bit ROM. The ROM produces the output as “00111”.

3.3 32 bit logarithmic shifter

The logarithmic shifter is the important piece in binary logarithmic converters as it supplies the mantissa part of the final value. An N-bit logarithmic conversion needs a logarithmic N-bit shifter to rotate the data from 0 to N-1 [11, 24, 25]. Here, the output is identical to the input term, which is shifted by a number of positions defined by the leading one position, and the direction of shifting is from the LSB to the MSB. In the above example, the shifter has to shit 7 bits as the characteristic is equaled to 7 and the output of the shifter is (101101100000000000000000000) ${}_{2}$ . Hence, from Eq. (7) in Section 2.2, the outcome using Mitchell’s algorithm is “00111. 101101100000000000000000000”. To improve accuracy in the Mitchell’s value an error-correcting circuit are proposed in [4, 5, 7] are used as shown in Fig. 3.

4. The proposed error-correcting algorithm

Depending on the provided logarithmic conversion methods, a trade-off exists between the precision obtained, delay, and hardware required for the correction circuit. Both [4, 5] is focused on using all the bits in the mantissa for modification. They were 27bits in the 32-bit logarithmic converter; thus, it requires a 27-bit error correcting circuit. Furthermore, these algorithms require mantissa to be multiplied with different slopes, which necessitates the addition of four additional blocks, one for each of the four regions. The binary logarithm’s great precision, which comes from Combet’s technique and Hall’s method systems, comes at the cost of speed, high power consumption, and hardware complexity. The correction circuit formed by SanGregory, unlike Combet’s method and Hall’s method, is portable and quick. It only uses the four most significant bits of the mantissa for approximation; nevertheless, it is less efficient than the other methods in terms of accuracy.

The main aim of this paper is to propose an algorithm for binary logarithm correction. This can be achieved with the circuits that have a low conversion error rate. In the proposed algorithm, it is suggested to use a few bits from the mantissa. The algorithm also offers to use the logarithmic value characteristic to choose the correction term for correction in the mantissa. For the reduction of error in Mitchell’s algorithm, the weighted average method is proposed. In this algorithm, the numbers are divided into successive two powers, as illustrated in Table 2.

Table 2
Illustration of proposed algorithm

$N$ decimal	$N$ binary	$\text{Log}_{2}(N)$ exact	$\text{Log}_{2}(N)^{\|}$ binary Mitchell approx	$\text{Log}_{2}(N)^{\|}$ Mitchell approx	Error	Average of error	$\text{Log}_{2}(N)$ proposed
1	00001	0.00000	000.0000	0.00000	0.00000	0.00000	0.00000
2	00010	1.00000	001.0000	1.00000	0.00000		1.00000
3	00011	1.58496	001.1000	1.50000	0.08496	0.0849	1.58490
4	00100	2.00000	010.0000	2.00000	0.00000		2.00000
5	00101	2.32193	010.0100	2.25000	0.07193		2.32141
6	00110	2.58496	010.1000	2.50000	0.08496	0.0714	2.57141
7	00111	2.80373	010.1100	2.75000	0.05373		2.82141
8	01000	3.00000	011.0000	3.00000	0.00000	0.0644	3.00000
9	01001	3.16992	011.0010	3.12500	0.04492		3.18940
10	01010	3.32193	011.0100	3.25000	0.07193		3.31440
11	01011	3.45942	011.0110	3.37500	0.08442		3.43940
12	01100	3.58496	011.1000	3.50000	0.08496		3.56440
13	01101	3.70043	011.1010	3.62500	0.07543		3.68940
14	01110	3.80735	011.1100	3.75000	0.05735		3.89440
15	01111	3.90689	011.1110	3.87500	0.03189		3.93940
16	10000	4.00000	100.0000	4.00000	0.00000	0.0609	4.00000
17	10001	4.08746	100.0001	4.06250	0.02496		4.1233
18	10010	4.16992	100.0010	4.12500	0.044925		4.1859
19	10011	4.24792	100.0011	4.18750	0.060428		4.2484
20	10100	4.32192	100.0100	4.25000	0.071928		4.3109
21	10101	4.39231	100.0101	4.31250	0.079817		4.3734
22	10110	4.45943	100.0110	4.37500	0.084432		4.4359
23	10111	4.52356	100.0111	4.43750	0.086062		4.4984
24	11000	4.58496	100.1000	4.50000	0.084963		4.5609
25	11001	4.64385	100.1001	4.56250	0.081356		4.6234
26	11010	4.70043	100.1010	4.62500	0.075440		4.6859
27	11011	4.75488	100.1011	4.68750	0.067388		4.7484
28	11100	4.80735	100.1100	4.75000	0.057355		4.8109
29	11101	4.85798	100.1101	4.81250	0.0454810		4.8734
30	11110	4.90689	100.1110	4.87500	0.0318910		4.9359
31	11111	4.95419	100.1111	4.93750	0.0166960		4.9984

Let us consider a number $N$ ,

$\displaystyle A=\log_{2}(N)$ (19) $\displaystyle A^{|}=(\log_{2}(N))^{|}$ (20) $\displaystyle\textit{Error}=A-A^{|}$ (21) $\displaystyle A=A^{|}+\textit{Error}$ (22)

In each region, the deviation of Mitchell’s value from the exact value is calculated. The average deviation in each region is also calculated by excluding the terms with powers of two ( $2^{0},2^{1},2^{2},\ldots$ ). Let us assume the error in Eq. (22) equals the average value of deviation in each region.

$\displaystyle\textit{Error}\approx\textit{Average of Deviation}$ (23)

So Eq. (22) becomes

$\displaystyle A=A^{|}+\textit{Average of Deviation}$ (24)

The average values of the deviations are moved to the most significant one and represented as the characteristic of the logarithmic value, as shown in Table 3.

Figure 4.

Block diagram of proposed logarithmic conversion circuit.

Table 3

Correction term for different characteristic values

Characteristic	Correction term
0	0
1	0.085
2	0.0714
3	0.0644
4	0.0609
5	0.0591
6	0.0582
7	0.0578
8	0.0575
9	0.0574
10	0.0574
$>$ 10 and $<$ 32	0.0573

Figure 5.

Illustration of error correcting block.

Figure 6.

Illustration of an example using the proposed method.

Figure 7.

Comparison of the proposed approximation with exact and Mitchell’s approximation.

Figure 8.

Comparison of the proposed approximation with exact and Mitchell’s approximation.

The correction terms are chosen using the characteristic (k), which is then appended to the mantissa’s most significant eight bits. Table 2 shows an illustration of the proposed algorithm and an example illustration is shown in Fig. 6. The block diagram of the 32bit binary to a binary logarithmic circuit with the proposed algorithm is illustrated in Fig. 4. Unlike the algorithms mentioned above, the recommended error correcting circuit receives the input from the characteristic of the logarithm. The error-correcting block is illustrated in Fig. 5. Here, the correction terms in Table 3 are stored in the ROM. These correction terms are selected using 32 $\times$ 8 ROM with characteristics as a selection line. The proposed approximation is shown in Fig. 8. The segment of this Figure with 8 $<$ N $<$ 16 is presented in Fig. 8b. From Fig. 8a, it can be observed that the deviation between the proposed logarithmic curve and the exact logarithmic curve is low when compared to Mitchell’s algorithm. The proposed algorithm has a maximum error percentage in the interval [ $-$ 0.91, 0.57], and detailed error analysis is discussed in the following section.

5. Evaluation and analysis

To demonstrate the value of the proposed logarithmic converter, we compare its error % and hardware metrics to those of several estimated logarithmic converters in the present state of the art. These logarithmic converters include [3, 4, 5, 7]. As in the recent literature, works mostly focused on Mitchell’s logarithmic technique based multipliers [8, 9, 10, 11, 12, 13, 14, 15] and they tried to decrease the error in multiplier result. Still, they haven’t focused on logarithmic and antilogarithmic converters. This made the authors restrict their comparisons of proposed logarithmic conversion to Mitchell’s techniques [3, 4, 5, 7]. The main findings of the proposed work are as follows:

Table 4
Comparison of errors in binary logarithm algorithms

	Mitchell	Combet	Hall	Abed	Proposed
Mantissa regions	1	4	4	2	1
Mantissa bits used none	ALL	ALL	3	8
Max. +ve error	5.360536964	0.18494133	0.125844188	0.929876086	0.578754571
Max. -ve error	0	$-$ 0.26688618	$-$ 0.7182	$-$ 0.564373875	$-$ 0.910830509
Error range	5.360536964	0.45182751	0.844044188	1.49424996	1.489585081
Complexity of error circuit	None	Complex	Very complex	Moderate	Easy

Figure 9.

Hardware performance.

Table 5

Comparison of Hardware consumption of different logarithmic converters

DESIGN	AREA ( $\mu m^{2}$ )	POWER ( $\mu W$ )	DELAY (ns)	AD ( $fm^{2}.s$ )	PD (fJ)	PA ( $fm^{2}.s$ )
Mitchell	765	27.93	2.986	2.28429	83.399	21.3665
Combet	3720	158.46	11.097	41.2808	1758.43	589.471
Hall	7033	361.21	12.394	87.167	4476.84	2540.390
Abed	992	43.45	4.42	4.38464	192.049	43.1024
Proposed	802	38.97	4.223	3.38685	164.57	31.2539

Figure 10.

Comparison of hardware performance metrics of different algorithms vs peak error percentage.

The ROM based error-correcting circuit made the logarithmic converter’s implementation simple and improved the logarithmic converter’s speed compared with other circuits.

The area of the proposed logarithmic converter is reduced when compared to other proposed algorithms.

The proposed logarithmic conversion consumes less power when compared with the other methods.

The maximum error in the proposed work is 0.91% ( $<$ 1%), which can be tolerable for some applications at the cost of hardware.

The above-stated findings are explained briefly in the rest of the section.

5.1 Error analysis

The maximum error percentage achieved by using the proposed method ranges over $-0.91\leqslant E_{\textit{percent}}\leqslant 0.57$ , as shown in Fig. 8. The maximum error percentage value of the proposed method is 0.91%, which is less than 5.3605% for Mitchell, 1.5403% for SanGregory, 0.9299% for Abed’s 2-region, as shown in Table 4. The proposed approximation approach is better than all other methods. It offers a good degree of precision, taking into account the simplicity of the error circuit’s hardware and its significant effect on the overall delay and the amount of power consumed. This technique may be used to execute the binary logarithm correction circuit used for low-power applications. The comparison of different binary logarithm algorithms is illustrated in Table 4, and error percentages of these algorithms are depicted in Fig. 8.

5.2 Hardware analysis

The 32-bit Logarithmic converter using different algorithms is described using Verilog HDL at the gate-level, and the corresponding designs are synthesized using a CADENCE 6.1 EDA tool with 90 nm CMOS technology. The hardware performance metrics such as area occupied, power consumption, critical path delay, area delay product (AD), power delay product (PD), power area product (PA) are evaluated for different algorithms used for logarithmic conversion. These performance parameters are listed in Table 5. It is observed from the tables that the proposed method occupies 78.45%, 88.6%, 19.2% less area, consumes 75.4%, 89%, 10.3% less power, and 62%, 66% and 5% faster when compared with Combet et al. [4], Hall et al. [5], and Abed et al. [7] respectively. The comparison of hardware performance metrics with different algorithms are shown in Fig. 9. Figure 10 shows the comparison of different algorithms’ hardware performance metrics with respect to the peak error percentage. From the above results, it can be observed that the proposed logarithmic converter consumes less power and occupies less area along with less peak error when compared with other algorithms. The proposed method serves as the best alternative in the areas where low power and fast logarithmic converters are used.

6. Conclusion

Simple error correcting circuit is used to create a 32 bit binary to binary logarithmic converter in this paper. We partitioned the numbers as powers of two in the proposed approach and estimated Mitchell’s deviation from the actual outcome. The weighted average of deviations in each partition is used to correct the terms in Mitchell’s output, making the error percentage reduce from 5.36% in Mitchell’s to 0.91%. The logarithmic converter is less difficult and easier to implement than existing approaches since the correction terms are stored in ROMs. When hardware complexity is taken into account, the proposed method appears to be the best way among the existing error-correcting algorithms.

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Hardware efficient circuit for low error logarithmic converter

Abstract

Keywords

1. Introduction

2.2 Base two logarithm of binary number using Mitchell’s algorithm

2.3.1 Combet et al. correction

3.2 32 × 5 bit ROM

3.3 32 bit logarithmic shifter

4. The proposed error-correcting algorithm

Table 2 Illustration of proposed algorithm

Table 4 Comparison of errors in binary logarithm algorithms

5.2 Hardware analysis

6. Conclusion

References

3.2 32 $\times$ 5 bit ROM

Table 2
Illustration of proposed algorithm

Table 4
Comparison of errors in binary logarithm algorithms