Low noise amplifier with resistive and capacitive feedback for 2.4 GHz RF receiver front end

Abstract

Low Noise Amplifier (LNA) is the front end block in RF receiver that improves the performance of wideband receivers. These receivers need LNA with high linearity to protect its signals from out-of-band interferences. Linearization is a key factor in LNA that maintains linear operation in the presence of large distracting signals. Existing techniques in LNA design are optimum gate biasing, MGTR, body biasing, noise cancellation, feed forward, derivative superposition, and modified DS technique. The key challenge of RF LNA circuit is to attain high gain and better noise performance with low power consumption without affecting linearity of LNA. This paper presents several linearization methods used in CMOS LNA. These are (1) post distortion, (2) capacitive feedback, (3) resistive feedback, and (4) current reuse technique. We also propose a new method for LNA with resistive and capacitive feedback. In this paper, different LNA circuits and proposed LNA are simulated using 90 nm CMOS technology. Reuse of bias current and two stage coupling by single current source approach in the proposed current reuse LNA with resistive (R) and capacitive (C) feedback yields better gain of 15.2 dB, noise figure of 2.17 dB and power consumption of 7.1 mW with respect to other techniques. The outputs obtained are compared with other similar works. These results validate that the proposed LNA is practically feasible for wireless sensor network applications.

Keywords

Low noise amplifier (LNA)single ended LNA resistive feedback capacitive feedback post distortion linearization technique (PD-LNA)current-reuse technique

1. Introduction

Linearity in an amplifier aims to increase the input signal power level which in turn is related to gain of an amplifier. Post distortion and current reuse are two popular techniques to improve linearity in LNA. The LNA is widely used in ultra wide band applications, mobile WiMAX, WLAN, GPS, Zigbee, cognitive systems [19,34] and learning engines [18]. Literature surveys have revealed the importance of improving linearity in LNA.

The authors in [44] used single ended LNA with second order ultra low distortion technique for obtaining low noise figure and low power consumption for WLAN applications. A similar single ended LNA was reported in [51]. The LNA at 900 MHz and 1 V supply for wireless hearing aids and low power applications were analyzed in this work [51]. Noise analysis is performed in [6] using SPICE environment. Single ended LNA is used in this work; however filter impedances and antenna design impedances have not been given attention. A complementary source follower [29] is added to improve the linearity as well as to obtain better IIP2 and IIP3. In this work, by inclusion of post distortion technique LNA further achieves noise figure performance. LNA with post linearization is reported in [13] for improving image rejection ratio (IRR) and third order input intercept point (IIP3). In this work LNA with and without notch filter are analyzed based on inter modulation third order compensator (IMD3) for better linearity and image rejection ratio (IRR). LNA with active feedback which is tunable and post distortion gives better linearity for ultra wideband applications [20], where this tunable active feedback compensates the degradation of bandwidth and gain.

By parallel R and C feedback, linearity is improved in this work. This arrangement also gives superior behavior in terms of noise figure, group delay, gain flatness and stability of LNA in UWB frequency range [20]. A small inductor connected in series with gate terminal [28], however a resistive feedback used in this work will increase trans conductance and compensate gain loss which in turn gives flat gain and higher bandwidth for LNA. A similar Pre distortion technique with inductor at auxiliary transistor is highlighted in [33]. The focus of this work is to improve input matching, gain, noise performance and third order input intercepts point (IIP3). A second order inter modulation distortion cancellation technique [30] is used in dual loop feedback which stabilizes input return loss and allows reasonable low power consumption. In this work, a peaking inductor is used to enhance the bandwidth of LNA.

The inclusion of linearization approach for input matching within capacitor cross coupled in a common gate configuration is done by authors in [32], this arrangement is evaluated based on third order input intercept point (IIP3). A transistor in feedback path is used in this work for better noise cancellation and enhancing the quality of LNA. Cross coupled dual capacitor feedback for multiband multimode wireless communication applications to increase the trans conductance and negative impedance techniques to correlate the input impedance and trans conductance matching between the transistors were reported in [9]. In this work, a new method for LNA with Current bleeding technique is used. The emphasis of this technique is to avoid the use of large resistor loads and the necessity of bulky inductors in the design. In [3], common gate LNA takes the advantage of dual capacitive cross coupling and shunt feedback for bandwidth extension of capacitors and to reduce power consumption. In [9], negative impedance techniques are used along with dual capacitor cross coupled feedback in common gate LNA for low power consumption and to boost the input trans conductance, thereby noise figure is reduced by the negative impedance technique used in this work. A capacitive feedback matching network technique in LNA helps for better gain, noise figure, reverse isolation, input and output return losses, however active feedbacks decrease the linearity of source follower circuits [58].

Current reuse technology for low power consumption and multiple gated transistor schemes to improve linearity of LNA are highlighted in [11]. Feedback with balanced topology technique is reported in [48] for WLAN applications to attain high gain and low noise figure. Gm boosting with folded cascade LNA [42] with modified derivative superposition to obtain high linearity. Load resistors are replaced with active loads in CG, CS stages as double feedback structure [4] to boost the gain and decrease noise figure are reported in this paper. Investigation is carried out on generative power consumption of P systems using one sided and erasing contextual rules [41]. Zigbee networks with characteristics of low power consumption and high security is suitable for wireless sensor networks in smart home automation [64]. As wireless sensors not used in cloud, a scalable resilient power paradigm are concentrated [10]. Effect of body bias and temperature on drain current is carried out in [14]. A comparative study [27] of 180 nm and 350 nm in NMOSFETS in frequency range of (1–100K) Hz. Custom ESD structures [49] is utilized for minimizing noise figure in tuned low noise amplifier.

In this paper, a current reuse amplifier with R and C feedback based LNA technique has been proposed. The novelty lies in the bias current of first stage amplifier, which is reused for the gain of second stage amplifier. Coupling of two stages is changed suitably by a single current source. The main motivation for using this approach is the capability of R and C feedback, drain inductor in yielding high gain, and low noise figure. Experimental results show promising results for the proposed approach. The rest of this paper is organized as follows: Section 2 gives an overview of two conventional techniques for LNA, Section 3 illustrates the various methods for linearity in LNA and the proposed method, Section 4 presents the experimental results and discussions, and Section 5 concludes the work.

2. Overview of conventional linearization techniques for LNA

This section briefly explains

Single Ended LNA

Post Distortion Linearization Technique

Fig. 1.

Diagram of single ended LNA.

2.1. Single ended LNA

The circuit diagram of single ended LNA [44] is shown in Fig. 1. Resistor $R_{S}$ represent the source impendence and is used for impedance matching of the circuit. The cascading transistor $M_{2}$ is used to cut down the influence of $M_{1}$ transistor’s gate to drain capacitance effect. Further, it is used to reduce the merging of the tuned input with the tuned output. The drain inductor $L_{2}$ is used to achieve high gain for circuit by vibrating it with the drain of the transistor $M_{2}$ .The input matching is done by the source degeneration inductor $L_{3}$ . The gate inductor $L_{1}$ should be selected in such a way that it gives desired input resistance. The $R_{1}$ , $R_{2}$ and $M_{3}$ transistor forms a bias circuit. The transistor $M_{3}$ is mainly used to form current mirror with the transistor $M_{1}$ and its width is small compared with $M_{1}$ transistor. By adjusting $R_{2}$ value the fixed operating point can be acquired. The $C_{1}$ and $C_{2}$ represent DC blocking capacitors.

Calculation of gate-oxide capacitance ( $C_{ox}$ ) $\begin{array}{l} (1) & C_{ox} = ε_{ox} / tox \\ (2) & ε_{ox} = ε_{o} * ε_{r} \end{array}$ Where $\begin{array}{l} ε_{ox} = permittivity of gate oxide \\ tox = Thickness of gate oxide \\ ε_{o} = Free space permittivity \\ ε_{o} = 8.854 * 10^{- 12} F / m ε_{r} = 3.9 \end{array}$ Hence we get, $\begin{array}{l} ε_{ox} = 3.45 * 10^{- 11} F / m \end{array}$

So $\begin{array}{l} C_{ox} & = 3.45 * 10^{- 11} / 4.1 * 10^{- 9} \\ = 8.42 * 10^{- 3} F / m^{2} \end{array}$

2.2. Post distortion linearization technique

An active post distortion technique applied to dual band cascade in common gate configuration LNA [65] to decrease noise figure, input reverse isolation and increases power gain and input intercept point (IIP) for high bandwidth applications. Post distortion with active feedback in differential LNA [66] attains noise cancellation and high input intercept point (IIP) for high frequency applications. Using negative feedback in inductor less common gate LNA [31] to break the tradeoff between transconductance (gm) and input matching; current reuse and negative feedback together gives reduced noise figure and power consumption along with high gain for the LNA.

A linearized UWB CG-LNA [23] is proposed. In this work, an auxiliary PMOS being utilized to ingest the second-and the third-arrange nonlinear streams of the LNA over a wide recurrence range. This LNA accomplishes great linearity and data transmission, and is appropriate for high-linearity UWB applications [52]. It is implemented in 0.18 CMOS Technology and shows that IIP3 and IIP2 have around 9 dB and 6.9 dB enhancements in expansive recurrence. The LNA [23] also obtains a gain between 9.6–12.6 dB and NF of 3.9–5.8 dB in the frequency range of 1.6–9.7 GHz with a power dissemination of 10.6 mW under a 1.8 V control supply. Noise and distortion are reduced, IIP2 is improved in [1] by exploiting the conventional combination of CG with CS and using both PMOS and NMOS in CG stage.

CMOS LNA utilizes the APD technique [39] to increment linearity execution. The hypothesis of the APD technique is implemented for low and high recurrence applications; the LNA is also actualized for CDMA cell band application and shows great concurrence with diagnostic outcomes. The results in [39] proves that it can move forward with linearity execution, little noise figure and gain loss penalty, the LNA also attains 1.2 dB NF, 16.2 dB gain, while devouring 12 mA current from 2.6 V supply voltage.

Post-linearization method for the cascode corresponding metal oxide semiconductor (CMOS) for LNA is shown in [40]. It uses an extra collapsed cascode positive-channel metal oxide semiconductor field-impact transistor for sinking the third-arrange intermodulation twisting (IMD3) current created by the normal source arrange, while limiting the debasement of gain and noise figure. This method in [40] is used to upgrade the linearity of CMOS LNA. When implemented in $0.18 μ m$ technology, the LNA accomplished $+ 13.3 -dBm$ IIP3 with 12.8-dB increase, 1.4 dB NF at 2 GHz devouring 8 mA from a 1.8-V supply.

The theoretical idea behind post distortion linearization technique (PD-LNA) is validated in [23,39] where the initial transistor’s on-linearity is neutralized by using the secondary transistor’s non-linearity.

Calculation of optimum width of the transistor $M_{1}$ $\begin{matrix} (3) & W_{opt} = 1 / (3 . C_{ox} . ω . L . R_{S}) \end{matrix}$ Where $\begin{array}{l} C_{ox} = Capacitance of the gate oxide \\ ω = Angular frequency \\ L = Length of the device \\ R_{S} = Source Resistance \end{array}$ The advantages of PD-LNA include [40,63].

It helps to reduce the impact of input matching by fusing the secondary transistor to the output of the initial device compared to using it to the input of the initial device.

Achieves strong distortion cancellation.

The circuit diagram of PD-LNA is shown in Fig. 2. PD-LNA technique [65], the power consumption of the circuit is very large by the additional usage of the components.The main drawback is that circuit complexity increases.

Fig. 2.

Circuit diagram of PD-LNA.

Input Impedance of single ended LNA shown in Fig. 1. at resonance frequency is $\begin{matrix} (4) & Z_{i} = (\frac{g_{mM 1} L_{s}}{C_{gs}}) + j ω_{o} (L_{3} + L_{1}) + \frac{1}{j ω_{o} C_{gs}} \end{matrix}$ Where $g_{mM 1}$ is transconductance of M1 transistor In Fig. 2. PD-LNA; M3 transistor acts as biasing circuit and M4 transistor acts as post linearization circuit. The collector current at M1 is $\begin{matrix} (5) & i_{c} = g_{mM 1} v_{be 1} + g_{2} v_{be 1}^{2} + g_{3} v_{be 1}^{3} \end{matrix}$ Where $g_{mM 1}$ is transconductance of M1 transistor and $g_{2}$ , $g_{3}$ are first order and second order derivatives of $g_{mM 1}$ , $v_{be}$ is the base to emitter voltage of M1 transistor. The collector current at M4 is $\begin{matrix} (6) & i_{c} = g_{mM 4} v_{be 4} + g_{2} v_{be 4}^{2} + g_{3} v_{be 4}^{3} \end{matrix}$ Where $g_{mM 4}$ is transconductance of M4 transistor and $g_{2}$ , $g_{3}$ are first order and second order derivatives of $g_{mM 4}$ , $v_{be 4}$ is the base to emitter voltage of M4 transistor. The ouput current in post linearization LNA is $\begin{matrix} (7) & i_{output} = (g_{m} - \frac{g_{mM 4}}{g_{mM 2}}) v_{1} + (g_{2} - \frac{g_{mM 4} g_{2}}{g_{2}} + \frac{g_{mM 4} g_{m}^{2}}{g_{m 2}^{2}}) v_{1}^{2} + (g_{3} - \frac{g_{mM 4} g_{3}}{g_{m 2}} + \frac{2 g_{2 M 4} g_{m} g_{2}}{g_{m 2}^{2}} - \frac{g_{m}^{3} g_{3 M 4}}{g_{m 2}^{3}}) v_{1}^{3} \end{matrix}$ Where $g_{m}$ is transconductance of M1 transistor and $g_{2}$ , $g_{3}$ are first order and second order derivatives of $g_{m}$ .

The challenge in LNA is to obtain high gain, low noise figure, high/flat band width and low power consumption. In this paper, we carried out the design and analysis of new method with resistive feedback and capacitive feedback in current reuse amplifier for obtaining low noise figure and high gain in LNA for receiver front end using 90 nm CMOS technology in cadence. The novel idea of this work is that the bias current of first stage is used for increasing the gain of amplifier’s second stage. Coupling of two stages is done by a single current source. R and C feedback, drain inductor in the proposed LNA can lead to high gain, low noise figure. Table 1 depicts various LNA approaches to improve the performance.

Table 1

Various techniques to improve LNA performance

Ref paper no:	Improve linearity	Increase gain	Decrease NF	Low power consumption	Flat gain/higher bandwidth	Techniques to avoid bulky inductors/large resistor loads
[4,9]	–	Cross coupled dual capacitor feedback, double feedback structure in CG, CS stages by replacing load resistors with active loads	Negative impedance techniques, double feedback structure in CG, CS stages by replacing load resistors with active loads	–	–	Current bleeding technique
[17,26,35]	Notch filter	Bias optimization-low drain bias plus optimum gate voltage scheme	Forward body bias, modified current reuse technique, bias optimization-low drain bias plus optimum gate voltage scheme	Self forward body bias	–	–
[24,25]	Resistive feedback and inductive source degeneration techniques	CS amplifier with shunt-shunt feedback as output buffer	CS amplifier with shunt-shunt feedback as output buffer	–	–	–
[61]	–	Inductive inter-stage and modified input matching circuitry	–	Inductive inter-stage and modified input matching circuitry	–	Cascade configuration with parallel LC inter-stage gives good output swing
[53,62]	–	Differential stage on top of CG–CS stage, single differential topology, Gilbert down conversion mixer topology	Differential stage on top of CG–CS stage, Single differential topology,Gilbert down conversion mixer topology	–	Staggered tuning on CG–CS stage	–
[2 ,11 ,21 ,24]	–	–	–	Current reuse along with noise cancellation techniques	–	–
[26]	–	Inductive peaking splitting load in current reuse	Inductive peaking splitting load in current reuse	–	–	–
[15 ,22]	–	Inductive degenerated cascade LNA structure, High Q transformers, inductors	Inductive degenerated cascade LNA structure, High Q transformers, inductors	Down conversion mixer for low power Zigbee applications, Coupled switching mixer stage	–	–
[24 ,43]	–	Noise cancellation	Noise cancellation	–	–	–
[11 ,54]	Multiple gated transistor with gm boosting technique	–	–	–	Shunt peaking	–
[42]	Derivative superposition, modified derivative superposition scheme, harmonic termination network, Gm boosting with folded cascade LNA	–	–	Folded cascade LNA	–	–

3. Proposed methodology

3.1. Capacitive feedback technique

Using capacitive-peaking strategy [12] to expand the transmission capacity of a transimpedance enhancer has been proposed, where the peaking capacitance in the Butterworth-sort transimpedance amplifier configuration has been determined. Using this approach, the 3-dB data transfer capacity of the transimpedance enhancer is improved from 1.1 to 2.3 GHz without relinquishing its low-frequency gain by this C-peaking strategy. A SiGe HBT ultra-wideband (UWB) LNA [45] is implemented, which exploits the miller impact for UWB input impedance coordinating and the inductive shunt–shunt feedback system for data transfer capacity augmentation by post zero cancellation. This LNA takes the advantage of miller effect and inducting shunt-shunt feedback to attain level and high UWB. Good input coordinating, gain, NF, and stage linearity exhibitions were accomplished by this SiGe UWB LNA.

The idea of capacitive feedback technique [16] is as below. $\begin{matrix} (8) & C_{f} = \frac{2 * W_{opt} * C_{ox} * L}{3} \end{matrix}$

The advantages of capacitive feedback technique include [12,45].

A capacitor is placed based on shunt-shunt feedback composition and gives matching impedance at the input irrespective of the noise.

The noise in the gate inductor is removed using this technique.

The circuit diagram of capacitive feedback is shown in Fig. 3. Capacitive feedback technique in [58] helps to gain reduction along with large power consumption.

Fig. 3.

Circuit of capacitive feedback LNA.

3.2. Resistive feedback technique

A new modified resistive feedback [7] structure for planning wideband LNA is proposed. In these systems along with feedback a source supporter, R–C input arrange, a peaking inductor inside the feedback circle, and balance capacitors are used. Two LNAs, namely LNA1 and LNA2 created using TSMC computerized 90-nm CMOS innovation. Both chips were implemented on board utilizing chip-on-board bundles with ESD diodes included at the sources of info and yields. LNA1 attains a 3-dB data transmission of 9 GHz with 10 dB of energy gain and a base NF of 4.2 dB. LNA2 attains a 3-dB transmission capacity of 3.2 GHz with 15.5 dB of energy gain and a base NF of 1.76 dB. The two LNAs have third-arrange inter modulation of 8 dBm and 9 dBm respectively. Their energy utilizations are 20 mW and 25 mW respectively with a 1.2-V supply.

Wideband LNA with shunt resistive-feedback [8] arrangement and inductive-peaking is proposed for wideband information coordinating broadband power gain and level (NF) reaction. This LNA is simulated using 180 nm CMOS and measured outcomes prove that power gain is more prominent than 10 dB and information return misfortune is beneath – 10 dB from 2 GHz to 11.5 GHz. The IIP3 is around $+ 3 dBm$ , and the NF ranges from 3.1 dB to 4.1 dB over the band of intrigue.

The idea behind resistive feedback technique [7,36] is shown below. $\begin{array}{l} (9) & ω_{0} = 2 π f_{0} \\ (10) & R_{f} = 1 / ω_{0}^{2} C_{gs}^{2} R_{s} \end{array}$

The advantages of resistive feedback technique [8,57]:

Handles enormous undesired signals beyond much exaggeration.

Low noise performance with high sensitivity gain is achieved.

Matching of the networks is attained.

The circuit diagram of resistive feedback is shown in Fig. 4. Resistive feedback technique [50] is to improve the linearity, however amplifier gain is reduced.

Fig. 4.

Circuit of resistive feedback LNA.

The collector current without feedback in LNA is $\begin{matrix} (11) & i_{c} = g_{m} v_{be} + g_{2} v_{be}^{2} + g_{3} v_{be}^{3} \end{matrix}$ Where $g_{m}$ is the trans conductance and $g_{2}$ , $g_{3}$ are the first order and second order derivatives of $g_{m}$ respectively The collector current with resistive feedback in LNA is $\begin{matrix} (12) & i_{c} = \frac{g_{m}}{1 + β g_{m}} v_{be} + \frac{g_{2}}{{(1 + β g_{m})}^{3}} v_{be}^{2} + \frac{1}{{(1 + β g_{m})}^{4}} (g_{3} - \frac{2 g_{2}^{2}}{g_{1}} \frac{β g_{m}}{1 + β g_{m}}) v_{be}^{3} \end{matrix}$ Where $g_{m}$ transconductance is given by $\begin{matrix} (13) & g_{m} = μ_{n} C_{ox} \frac{W}{L} (v_{gs} - v_{th}) \end{matrix}$ The impedance of resistive feedback in LNA is $\begin{matrix} (14) & Z = \frac{C_{gs} + C_{gd}}{S C_{gs} C_{gd} + (C_{gs} + C_{gd}) (\frac{1}{R_{f}} + \frac{1}{R_{ds}}) - g_{m} C_{gd}} \end{matrix}$ The noise factor in capacitive feedback LNA shown in Fig. 4. is $\begin{matrix} (15) & \begin{matrix} NF & = 1 + \frac{Υ}{α} \frac{1}{g_{m} . R_{s}} {{(| c | α \sqrt{\frac{δ}{5 Υ}})}^{2} + (R_{s}^{2} - s^{2} L_{3}^{2}) (\frac{1}{R_{f}^{2}} - \frac{α^{2} δ}{5 Υ} {(1 - | c |^{2})}^{2} s^{2} C_{1}^{2}) \\ - {(s C_{1} R_{s})}^{2} {[1 + | c | α \frac{δ}{5 Υ}]}^{2} + \frac{2 R_{s}}{R_{f}}} \end{matrix} \end{matrix}$ Where c is correlation coefficient, Υ is thermal noise coefficient and δ is gate induced noise factor.

3.3. Current reuse technique

LNA with modified complementary current reuse technique [17] along with forward body biasing in diode connected at MOSFET will improve noise performance and notch filter increases linearity for medical applications. Current reuse and noise cancellation techniques [24] are used for high gain and low noise figure, resistive feedback and inductive source degeneration techniques used for good impedance matching at the input. Inductive inter-stage and modified input matching circuitry [61] to attain high gain and low power consumption. A differential stage and staggered tuning on the top of common gate-common source stage [53] gives increase in bandwidth along with high gain, low noise figure and distortion in transistor input matching. CS amplifier with shunt-shunt feedback as output buffer gives low noise figure and high gain, power reduction is achieved using current reuse technique [25].

Current reuse along with noise cancellation [2] techniques together contribute to power optimization by obtaining phase difference between noise and signal. LNA with current reuse common source cascade configuration [37] gives gain of 9.5 dB and noise figure of 5 dB using 180 nm technology. Inductive peaking with splitting load in current reuse technique [26] is used to obtain high gain and low noise figure, self forward body bias gives low supply voltage consumption. Bias optimization scheme [35] with low drain bias and gate voltage will increase the gain and decrease noise figure, circuit area can be reduced by 3-D helical inductors. Ultra low power and ultra low voltage fully differential cascade LNA [15] structure is implemented for Zig bee applications using 130 nm technology. Current reuse with high Q inductors, transformers and a coupled mixing stage together [22] gives high gain, low noise figure. Single differential topology and gilbert down conversion mixer topology [62] which have matching network helps in high gain, low noise amplifier. Noise cancellation technique [43] increases transconductance boosting and decreases noise figure. Noise cancellation with current reuse [21] decreases the need for high power. Multiple gated transistor with transconductance boosting technique increases linearity of LNA, along with shunt peaking for extending bandwidth in [54].

In current reuse method, the load is biased by using the current produced by the driver transistor. It is advanced in two facts [38,46,60]:

It helps to decrease the overall power usage in the circuit helps to attain modest gain.

Minimum voltage is applied throughout the circuit.

The conventional current-reuse technique is shown in Fig. 5. As in [5,56].

Fig. 5.

Circuit implementation of current-reuse LNA.

The channel width of input transistor must be optimum to achieve better noise performance and it is calculated as $\begin{matrix} (16) & W = \frac{3}{3 ω L C_{ox} R_{s} F_{op}} \end{matrix}$ Where $R_{s}$ is source resistance, $C_{ox}$ is oxide capacitance and $F_{op}$ is operating frequency. Gate width of M2 transistor is half of the gate width of M1 transistor. Gate to source capacitance of M1 transistor is given by $\begin{matrix} (17) & C_{gsM 1} = \frac{2}{3} W_{M 1} L C_{ox} \end{matrix}$ Where $W_{M 1}$ is the channel width of M1 transistor

Current-reuse technique [59] implemented using cadence in 180 nm technology, the circuit obtains high linearity however the gain reduction occurs at 5.4 GHz frequency band.

3.4. Proposed current reuse LNA with capacitive and resistive feedback

In RF circuit the low noise amplifier is located as the first component which is used to amplify the received input RF signal. The LNA should be adeptly linear to vanquish the interference. Moreover, it should able to give high gain sensitivity. The requirement for wireless standards such as cell phone has increased in the client market, which demands the designer to establish a LNA with high linearity in order to minimize the interference. While choosing a linearization method one of the important things we should consider is that the method chosen should be simple and reliable. We proposed a new technique with resistive and capacitive feedback in current reuse LNA for obtaining better noise figure and gain compared to existing methods. Also the proposed LNA can be used to solve RF tracing problem in SDR and for reducing the economically impractical PCB size.

Fig. 6.

Circuit of proposed current-reuse with R and C feedback method.

The 2.4 GHz current-reuse low noise amplifier (LNA) with R and C feedback circuit diagram is shown in Fig. 6. The Lg, Ld and LS are indicated using the spiral inductors. The gate inductor is shown as Lg. The input capacitance side effect is spurned by using Lg. The Ls is used for input matching. The degeneration inductor is indicated using Ls. Inductor Ld is the drain inductor that attains a high performance LNA by increasing its gain. Transistor $M_{2}$ is used to shrink the communication of tuned input with the tuned output and also it diminishes the gate to drain effect of $M_{1}$ . The two resistors $R_{1}$ and $R_{2}$ followed by the transistor $M_{3}$ is used to shrink the power utilization by assembling a bias circuit. The capacitor $C_{coupling}$ is used to permit the coupling of two gain stages as it is placed from M1 drain to the gate of M2. The inductor L1 acts as amplifier stage load and capacitor $C_{pass}$ indicate the bypass capacitor. The current-reuse technique is used in this circuit. The two amplifier stages are coupled with a single current source, the bias current of the first level is reused for the second level of the gain stage. The $C_{in}$ and $C_{out}$ are the DC blocking capacitors. Transistor M3 acts as mirror circuit for M1 transistor.

Noise canceling technique is applied in the circuit. The signal current and drain thermal noise in CS transistors lead to noise current and both the signal current, drain noise reach the output node from different paths. These signal currents are in phase, but the two noise currents are out of phase by $180^{\circ}$ . Thereby noise current is attenuated at the output, and the desired signal current gets amplified. Thus the noise canceling technique act as feed-forward scheme. Such noise cancellation techniques can be applied only till 10 GHz frequency of operation to control the signal currents to be in phase. But for very high frequencies, noise cancellation techniques cannot keep the signal currents in phase and cannot satisfy the minimum noise margin requirements.

Assuming that the Miller capacitance of M1 transistor is small, and its effect in the circuit can be removed. Assuming the transistors M3 and M1 are identical. To achieve maximum loop gain, ensure constraints applied on M2 transistor feedback transconductance gm. The trans conductance of M2 transistor is given by $\begin{matrix} (18) & g_{mM 2} = \frac{4 {(s C_{gd})}^{2} - {(\frac{1}{r} - s C_{s})}^{2}}{2 s C_{gd}} \end{matrix}$ Where $\begin{matrix} (19) & C_{s} = C_{M 3} + C_{gdM 2} \end{matrix}$ $C_{gdM 2}$ is the gate to drain capacitance at M2 transistor. $\begin{matrix} (20) & C_{M 3} = C_{gsM 3} + C_{gdM 3} \end{matrix}$ Depending on parasitic of M3 and M1 transistors, the value of feedback transconductance/bias current is adjusted. If this constraint is satisfied then the loop gain increases to larger value. Input power from source to LNA is $\begin{matrix} (21) & P_{i} = \frac{R_{e} (Z_{i}) V_{s}^{2}}{2 | R_{s} + Z_{i} |^{2}} \end{matrix}$ Power gain of proposed LNA is $\begin{matrix} (22) & Gain = \frac{| R_{s} + Z_{i} |^{2} | V_{L} |^{2}}{R_{e} (Z_{i}) R_{L} | V_{s} |^{2}} = \frac{| R_{s} + Z_{i} |^{2}}{R_{e} (Z_{i}) R_{L}} | A |^{2} \end{matrix}$ Noise figure is increased by parasitic capacitances. Noise cancellation technique suppresses the nonlinear components of M1 which is also one of the benefits. Noise cancellation techniques are in general feed-forward schemes. The input signal passes through the transistors M1, M2, and M3 then to the output node, so the nonlinear terms of these transistors i.e. the transconductance gm contribute to the linearity of the circuit. The noise figure is given by $\begin{matrix} (23) & N = 1 + \frac{v_{n}^{2}}{4 K T R_{s} A_{v}^{2}} . \frac{{(Z_{i} + R_{s})}^{2}}{Z_{i}^{2}} \end{matrix}$ Where $v_{n}$ is the output noise voltage, $R_{s}$ is source resistance, $Z_{i}$ is input impedance, $A_{v}$ is the gain. A current reused structure is used to increase gain and noise cancellation by CS amplifier. Current-reused techniques and Noise-canceling are used to achieve low and flat NF. By employing the resistive feedback techniques and inductive source degeneration, wideband input matching is achieved over the bandwidth.

Fig. 7.

Schematic of single ended LNA.

4. Experimental results and discussions

The LNA with various linearization techniques was simulated using 90 nm RF CMOS technology. They are (1) post distortion (2) capacitive feedback (3) resistive feedback and (4) current reuse technique. And the proposed current reuse LNA with R and C feedback is also implemented in 0.09- $μ m$ CMOS technology. The simulated results are described in Figs 7–14, in which Figs 10, 12, 14 are gain and noise figures of C feedback LNA, R feedback LNA and proposed current reuse LNA with R and C feedback, respectively.

Fig. 8.

Schematic of PD-LNA.

Fig. 9.

Schematic of capacitive feedback LNA.

Fig. 10.

Noise figure and gain of capacitive feedback LNA.

Fig. 11.

Schematic of resistive feedback LNA.

Fig. 12.

Noise figure and gain of resistive feedback LNA.

Fig. 13.

Schematic of proposed current reuse with R and C feedback for LNA.

Fig. 14.

Noise figure and gain of proposed current reuse with R and C feedback for LNA.

4.1. Single ended LNA

The schematic diagram of single ended LNA is shown in Fig. 7. The noise factor or noise figure represents the noise performance of the LNA and is nearly 3.8 dB for single ended LNA and obtained a gain of 5.5. The power obtained for single ended LNA is around 4.8 mW.

4.2. Post distortion linearization technique

The schematic diagram of PD- LNA is shown in Fig. 8. The noise figure obtained for PD-LNA is around 3.4 dB and gain obtained for PD-LNA is around 8.7 dB. The power obtained for PD-LNA is around 14.5 mW.

4.3. Capacitive feedback technique

The schematic diagram of capacitive feedback LNA is shown in Fig. 9 and its gain and noise performance shown in Fig. 10. The noise figure obtained for capacitive feedback is around 5.1 dB and gain obtained for capacitive feedback LNA is around 4.13 dB. The power obtained for capacitive feedback LNA is around 6.1 mW.

4.4. Resistive feedback technique

The schematic diagram of resistive feedback LNA is shown in Fig. 11 and its gain and noise performance shown in Fig. 12. The noise figure obtained for resistive feedback is around 5 dB and gain obtained for resistive feedback LNA is around 8 dB. The power obtained for capacitive feedback LNA is around 1.98 mW.

4.5. Proposed current reuse technique with R and C feedback

The schematic diagram of current-reuse LNA is shown in Fig. 13 and its gain and noise performance is shown in Fig. 14. The noise figure obtained for current-reuse LNA is around 2.17 dB and gain obtained for current-reuse LNA is around 15.2 dB. The power obtained for current- reuse LNA is around 7.14 mW.

Gain remains constant in any component when it is operated within linear region. There exist cases where output is not amplified to the same level when input power is varied as the smaller signal. 1 dB compression point is obtained at this point where output varies for less than 1 dB for a range of variation in input power. Decrease in gain can be observed after this 1 dB compression point and further increase in input may destroy the component. $\begin{matrix} (24) & PO 1_{dB} = PI 1_{dB} + (G - 1) dBm \end{matrix}$ Where $PO 1_{dB}$ is the output 1 dB power, $PI 1_{dB}$ is the input 1 dB power and G is the gain of the component/device at which 1 dB compression point is being analyzed.

Non linear passive components like diode exhibit 1 dB compression points. However in amplifiers non linear and active components like transistors play role and exhibit the 1 dB compression points. In any device there exist further power levels which may destroy its operation.

4.6. Performance comparison of various linearization methods

Table 2 illustrates the quantitative analysis of the various LNA approaches. It shows the performance of low noise amplifier using various methods that includes single ended LNA, PD-LNA, Capacitive Feedback LNA, Resistive Feedback LNA and Current-Reuse LNA with R and C feedback. While considering the parameters like gain and noise figure, using resistive and capacitive feedback with current reuse technique LNA, we obtained a lower noise figure of 2.17 dB and enhanced gain of 15.2 dB which shows better performance compared to other linearization methods. The results in Table 2. demonstrates that the gain and noise performance of proposed LNA is better compared to other conventional LNA methods.

Table 2
Analysis of linearization methods ( $supply voltage = 1 V$ at 2.4 GHz frequency and 90 nm technology)

Parameters Single ended LNA Post distortion – LNA Capacitive feedback LNA Resistive feedback LNA Proposed current-reuse LNA with R and C feedback

Gain (dB) 5.5 8.7 4.1 8 15.2

NF (dB) 3.8 3.4 5.1 5 2.17

Power (mW) 4.8 14.5 6.1 1.98 7.1

Parameters	Single ended LNA	Post distortion – LNA	Capacitive feedback LNA	Resistive feedback LNA	Proposed current-reuse LNA with R and C feedback
Gain (dB)	5.5	8.7	4.1	8	15.2
NF (dB)	3.8	3.4	5.1	5	2.17
Power (mW)	4.8	14.5	6.1	1.98	7.1

Table 3

Comparative analysis with other works

Ref. paper	Frequency (GHz)	Gain (dB)	Noise figure (dB)	Power consumption (mW)	V_DD (V)	CMOS tech. ( $μ m$ )	Year	Applications
[47]	2.4	$> 10$	$< 2$	–	5	ADS Software	2013	WLAN
[31]	3.3	20.1	3.2	1.3	1.8	0.18 CMOS	2016	WSN
[4]	0.45–0.9	24	2.7	5.4	1.2	0.13 CMOS	2015	Biomedical
[21]	0.6–3.15	20.2	2.37	6	1.5	0.18 CMOS	2018	–
[62]	1.575	26.08	0.487	–	1.5	0.09 CMOS	2017	GPS
[24]	3–12	19.24	1.72	23.23	1.8	0.18 CMOS	2017	Ultra-Wideband
[28]	0.4–10.6	$9.5 \pm 0.9$	3.5	12	1.5	0.065 CMOS	2014	–
[48]	2.4	$> 10$	$< 2$	–	5	ADS Software	2013	WLAN
[15]	2.4	22.3	7.2	0.905	0.5	0.13 CMOS	2013	Zigbee
[35]	3–5	13.3	3.5-4.0	1.77	0.25	0.18 CMOS	2017	Ultra-Wideband
[33]	0.8–10.4	13.7	3	–	1.8	0.18 CMOS	2017	Ultra-Wideband
[32]	2.96	18.55	2.63	2.77	1.5	0.18 CMOS	2017	–
[20]	3.1–10.6	8.8–10.2	3.8-4.9	26	–	0.35 SiGe BiCMOS	2013	Ultra-Wideband
[13]	17	16.5	4.58	2	1.8	0.18 CMOS	2010	–
[26]	3.1–10.6	17.8	4.8	9.67	1.2	0.18 CMOS	2014	Ultra-Wideband
[25]	–	13.2	3.33	9.3	1.5	0.18 CMOS	2013	Ultra-Wideband
[65]	3.5	13.2	3.9	9.36	1.2	0.13 CMOS	2014	Mobile WiMAX
This work	2.4	15.2	2.17	7.1	1	0.09 CMOS	–	WSN

Table 3. Show comparative analysis with other works. Table 3 summarizes the performance of recently published LNAs by 0.18- $μ m$ CMOS, 0.13- $μ m$ CMOS, 0.09- $μ m$ CMOS and 0.18- $μ m$ SiGe HBT technologies. Authors in [13] used post distortion technique in LNA at 17 GHz and obtained a gain of 16.5 dB, but high noise figure of 4.58 dB which is not preferable. Gain and noise performance of proposed LNA shows the feasibility of the proposed LNA to be used in wireless sensor network applications. However, the authors in [24] used noise cancellation in current reuse LNA at 3–12 GHz to obtain a gain of 19.24 dB and low noise figure of 1.72 dB, but the drawback is that the LNA need very high power consumption of 23.23 mW. Post distortion LNA in [65] and common source topology in current reuse LNA in [25] achieves a gain of 13.2 dB, but obtained high noise figure of 3.9 dB and 3.33 dB respectively with power consumption of 9.3 mW and above. The proposed work in our paper, by reusing bias current approach achieves noise figure of 2.17 dB and enhanced gain of 15.2 dB at power consumption of 7.1 mW which shows better performance comparatively.

Power dissipation in LNA can be reduced by incorporating special cares in circuit configuration and design steps. Low power RF designs use current reuse technique for DC power reduction. RF designs using current reuse configuration comprises of a CS stage followed by a cascode stage. However transistors with low transconductance gm cannot be used for operation in very high frequencies, and it demands high transconductance gm transistors as there exists increased losses in various parts of circuit. Trans-conductance CMOS transistors can be decreased by decreasing drain current and it leads to. gm-boosting techniques can be used to increase total gm, without increasing Id, the drain Current. Active load in NMOS drain can give high load resistance in RL of LNA without much dissipation of DC power. However, parasitic capacitances and high load resistance in the output node can limit the maximum frequency. For example, such problems can lead to limiting the unity gain of resistive-load to 15 GHz in a differential pair using CMOS 90 nm technology. This problem can be solved using inductive load to absorb parasitic capacitance.

Usage of passive inductors leads to increase in chip area. To overcome such problems, passive inductors can be substituted with active inductors and obtain high-Q inductors. LNA can be designed in small chip area by using active inductors. It further leads to limited frequency of operation. Hence inductor-less LNA can be designed for operating up to 10 GHz frequency.

We believe the layout of our proposed LNA should be considered in future work. It could then be sent to fabrication. However, if there is any mistake, e.g. in the layout for input matching, the layout will not automatically check to correct such errors. Such mistakes will further lead to deviations in the measured values. Before S parameter is being measured, calibration is required using any of the methods such as through reflect line (TRL), short-open load through (SOLT) and line reflect match (LRM). LRM+ is another calibration method which combines both TRL and SOLT.

S parameter analysis and the power gain obtained can speak of the accuracy of the design. Reverse isolation in LNA can state the stability of the design.

Noise figure measurement can be done using standard noise figure analyzer. Other methods for noise figure measurement are gain method and Y factor method. $\begin{matrix} (25) & Noise Figure = P_{o} - (- {ND}_{amb} + 10 log (BandWidth) + Gain) \end{matrix}$

$P_{o}$ is the noise power at output, ${ND}_{amb}$ will be $- 174 dBm/Hz$ the noise density for ambient noise ( $290^{\circ}$ ) Bandwidth and Gain of the system can be measured.

1 dB (P1 dB) compression point may be measured and is used to express linearity of the proposed LNA. For this, the input power (IP1 dB) and the output power (OP1 dB) are required.

5. Conclusion

In this paper, we proposed a Resistive and Capacitive feedback technique for Current Reuse Amplifier to improve the linearity of active feedback LNA. The associated theory and design steps were discussed. We showed that with the linearized R and C active feedback, LNA achieved a great improvement of gain and noise figure and also removed the limitations of conventional source follower on feedback. LNA with post-distortion was helpful to linearize the feedback LNA. The simulated results indicated that, at 2.4 GHz a high linearity with 15.2 dB gain and 2.17 dB noise figure was obtained in our proposed current reuse LNA with R and C feedback.

Layout of the proposed LNA will be considered in our future work. S parameter, Noise figure and linearity measurements etc can be done from the fabricated LNA using short-open load through (SOLT), Through reflect line (TRL) and line reflect match (LRM), LRM+ methods. Noise figure analyzer is used for NF measurement. DC power can be greatly reduced with the help of Current reuse in integrated circuits. Very low power applications need LNA with CMOS transistors. Low Q and other difficulties in CMOS technologies may be due to Passive inductors and it demand increase in the chip area. Using distributed elements in LNA leads to larger chip whereas using lumped elements in LNA help in achieving smaller chip area.

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