A VLSI DESIGN DESIGN-SYNTHESIS METHODOLOGY AT THE TRANSISTOR LAYOUT LEVEL

This paper presents a VLSI design synthesis methodology based on the Geometria language. Geometria is a context-free language, which has the ability of floorplanning, compaction and automated synthesis of functional blocks at various levels of a VLSI integration, starting from the transistor level. The Geometria methodology used in this paper deals with the design synthesis of VLSI circuit layout. More specifically it accepts various user's inputs such as stick diagram, circuit schematics, Boolean expression, netlists, or natural language text expressions, and produces automatically the desirable VLSI layout. One of the major characteristics of Geometria is that it is an automated process for VLSI layout placement and synthesis of blocks at various levels of integration.