Abstract
The traditional signal processing algorithms suffer from large execution delay for real time issues, therefore implementation of high speed algorithms is needed. The present work aims to implement multiplier less Savitzky Golay smoothing filter (SGSF) based on distributed arithmetic (DA) for pre-processing of Electro-oculographic (EOG) signals such that speed is increased along with reduction in chip area. The filter used should be efficient enough to remove the artifacts along with least deformation from the actual signal. Savitzky-Golay (SG) filter is widely employed in biomedical signal analysis but its fast and efficient implementation is not proposed yet for EOG analysis. SGSF is selected so that disease diagnosis using saccade detection of EOG signal can be done accurately. The efficiency of proposed filter is tested in terms of signal-to-signal-plus-noise ratio (SSNR) and real time computations. It is observed from the analysis that DA based architecture increases the processing speed, reduces the chip area and original features of filtered signal are preserved.
Introduction
Electrooculography is a technique for electrical measurement of corneo-retinal potential difference. An electrical field is created around the eye which changes with the movements in eye. An electric dipole is formed as the cornea and retina of the eye act as positive and negative poles. The bioelectrical signal so generated is known as EOG signal. EOG is an important tool in diagnosis of ophthalmological diseases because it is a non-invasive, inexpensive, quick and relatively accurate medical examination. Saccadic eye movements are widely used in fatigue and sleep study research for disease diagnosis [1]. Efficient hardware helps in fast decisions in intensive care units, during emergency medical services and can be used at remote places also. The aim can be achieved through reconfigurable computing architectures such as Field Programmable Gate Arrays (FPGAs). The hardware realization of human machine interface is also utilized in compact and mobile applications for completely disabled persons. Therefore automatic interpretation of EOG and high performance realization of EOG systems is still an issue of research. Smoothing and filtering is the most popular operations in biomedical digital signal processing. Digital filters improve results significantly [2]. The latest versions of real time monitors feature increased accuracy and resolution along with compact size and low power consumption. The application of FPGAs indicates that computing architecture can be explored to obtain a reconfigurable signal processing system.
Recently a lot of research is carried out to improve filtering of biomedical signals [3–5]. The digital filter with careful computation of coefficients, is suggested by various researchers to filter saccadic eye movements [6, 7]. Savitzky and Golay [8] suggested a filtering method (SG) and Schafer [9] analysed the design of SG filter. The filter is specified in the form of polynomials; whereas in conventional filter the stop band and passband frequency domain specifications must be mentioned. A recent application of SGSF is reported in eye movement recordings for smoothing EOG signals [10]. In other work SG filter has been used for artifact removal in electronystagmography (ENG) signal [11].
Digital filter used for initial processing must provide maximum noise removal capability with least signal deformation. Significant contributions are made by various researchers in the design of hardware based filters [12, 13]. Moreover efficient design can also be achieved using the techniques given in literature [14–16]. Performance of the filters may be enhanced by increasing the clock speed. Multiplication operation takes maximum hardware utilization thus making the chip area and power consumption high. Memory based architecture has higher throughput, less latency and low power consumption. The Look up tables (LUT) and shifters may be used in place of multipliers using distributed arithmetic based multiplier-less design. This reduces circuit complexity which further minimizes power dissipation and chip area [17]. This type of architecture is suitable for digital signal processing.
In the present work, SGSF is realized on reconfigurable and less complex hardware to improve the filtering process of EOG signal. The research work is organized as follows. Section 2 illustrates the method and material used in the work and Section 3 summarizes the theory of SGSF. The results and discussions are highlighted in Section 4 to validate and compare the results of multiplier less SGSF. Finally the research work is concluded in Section 5.
Method and material
The SGSF filter is first realized and compared with moving average filter (MAF) in MATLAB. SGSF is found to be more efficient in terms of SSNR in comparison to MAF. Therefore high speed and efficient implementation of SGSF is performed using Xilinx’s FPGA XC3S500E Spartan 3E starter kit as target device, for real time analysis. The main characteristics of FPGA are very high speed, programming capability, less cost and high reliability. It is a flexible general-purpose integrated circuit which can be updated any time. FPGA can be reprogrammed easily even after it has been implemented into a system. This kit has more than 10,000 logic cells [18], x16 data interface, 64 MByte (512 Mbit) of DDR SDRAM and 100+ MHz. The package is a 320-pin FPGA and clock has 50 MHz crystal oscillator. Real EOG is obtained from MIT-BIH Polysomnographic database [19] and given as input to FPGA device through test bench input. FPGA device performs SG filtering and the filtered output is shown in Fig. 1. Methodology for FPGA based implementation of SGSF for real EOG signal smoothing is as follows: Designed SGSF is tested and validated in MATLAB and coefficients are computed based on EOG application. Filter object is generated using precomputed coefficients and implemented as discrete time FIR filter. This unique filter object is exported in FDA tool and parameters are quantized in fixed point filter arithmetic. The Hardware description language (HDL) code is produced along with test bench file using direct form (for comparison purpose) and distributed arithmetic architecture. The synthesizable HDL code is validated using the desktop testing (test bench file) having EOG input.
Background theory
Savitzky golay smoothing filter
SGSF is a digital filter that can be implemented for a group of data to enhance the signal-to-noise ratio without contorting the signal. The subsets of consecutive data points are fitted using a low order polynomial with linear least square method and convolution of all the polynomials is then obtained [8, 9]. A series of k (a
j
, b
j
) points (j = 1,. . . k) is considered, where a is an independent variable and b is observed value. They are processed with a set of l convolution coefficients v
i
and are represented as:
DA is a popular multiplier-less structure for implementing FIR filters. DA computes the sum of products for FIR filters using LUTs, shifters and adders. These operations can be mapped effectively onto FPGA which results in easier implementation of DA architecture. Figure 2 shows the block diagram of basic structure of distributed arithmetic [17]. LUT reserves all the possible combinations of the sums of coefficients in three dimensional order. LUT stores all the possible combinations of the sum of coefficients in three dimensional order. Addition operation implements the filter functionality using LUT contents [17]. A register is utilized to shift the values again to arithmetic operation block.
In DA v i are the known set of filter coefficients and input b to the filter is represented in M-bit 2’s complement binary numbers.
We have
Substituting the result of Equation 2 in Equation 1:
The performance of SGSF is demonstrated on real EOG data of five subjects. The filter design index of SGSF is decided by the polynomial order N and window length F when used for smoothing applications. A desired cut-off frequency fc can be realized by different combinations of N and F [9]. The design parameters of SGSF in the present work are selected in such a way that denoising of raw EOG is performed efficiently. The designed filter has cutoff frequency of about 30 Hz for EOG applications. Magnitude response of the filter for N = 6 and F = 21 is shown in Fig. 3. The real EOG signal (Fig. 4) under consideration [19] is a recording of 10 s, having sampling rate of 250 Hz. The SGSF filtered data sets are analysed and compared with MAF in MATLAB. In case of real time signals performance of filter is evaluated using SSNR [20], therefore in the present work SSNR is considered.
It is assumed that smoothing algorithm removes the noise completely.
SSNR is given as:
The noisy and filtered EOG signals are shown in Fig. 4 and the corresponding SSNR of SGSF and MAF is shown in Fig. 5. The visual inspection confirms that MAF denoises the signal but waveform characteristics are not preserved. However in case of SGSF the denoised signal is completely preserved. It is also observed that SSNR is appreciably enhanced by SGSF in comparison to MAF.
After demonstration on MATLAB, the SGSF is implemented on FPGA with distributed arithmetic for pre-processing of EOG signal. Implementation of SGSF is easier than other filters used in EOG applications [14]. FPGA based SGSF with direct form architecture [13] is also implemented for comparison purpose. The performance of these hardware implementations are compared in terms of minimum time vis-à-vis critical path delay T min and resource indicators.
The critical path delay is calculated for hardware implemented structures, i.e. SGSF with direct-form [13] and SGSF with DA architecture. Both the structures operate at a clock speed of 13.22 MHz and 76.307 MHz respectively. The critical path delay for EOG signal denoising using SGSF with direct form is 76.307 ns. This critical path delay is further reduced to 13.105 ns using SGSF with DA architecture. The reduction in critical path delay enhances the clock rate and overall processing speed increases.
Resource indicators analysis
In this analysis four indicators are used to assess the performance of the hardware architectures. Slice Flip flops: Configurable logic blocks (CLBs) clusters assigned to function as memory. LUTs: CLBs assigned to perform as combinational logic. Occupied Slices: Slice is the basic building block in FPGA design. Each slice comprises a number of LUT’s, flip-flops, and carry logic elements which constitutes the logic of design. The “occupied slices” indicate the count of used and partially used slices. Total number of 4 input LUTs: It indicates Look up tables (LUT) which has four independent inputs.
The number of resources used in two different architectures is shown in Table 1. It is observed that number of used resources is significantly less in DA based SGSF than direct form architecture. Analysis of design via Hardware Description Language (HDL) simulation is performed using ISE Design Suite 12.3 (ISE Simulator: ISIM). Figure 6 shows the ISIM timing simulation of DA based SGSF denoising system for pre-processing of real EOG signal. Analog format of filtered EOG signal is shown in Fig. 7. It is revealed from the results that in case of DA based architecture chip area is reduced as number of FPGA resources used are less. Further the speed is significantly increased because of the mutilipler-less DA architecture in comparison to direct form architecture. The SGSF is successfully implemented on FPGA based direct form and distributed arithmetic computing architecture.
Conclusion
The present work focuses on the application of SGSF on distributed arithmetic based reconfigurable computing architecture for processing of real time EOG signals. The SGSF is first demonstrated using MATLAB to validate the performance of filter in terms of SSNR. It is observed from the results that SGSF shows better performance as compared to MAF. Hence SGSF is implemented in DA based reconfigurable structure which provides high speed and cost effective solution. The DA based architecture is multiplier less and utilizes less FPGA resources as compared to direct form architecture. Hence the proposed architecture increases the processing speed significantly and actual characteristics of signals are also retained correctly.