The optimal geometry parameters and impact of parasitic capacitance and resistance of sub-14nm SOI multi-fin FinFETs

Abstract

Nowadays FinFETs integrated into complex applications can fulfill the demand of new technology and make chips that can compute faster. Simultaneously various novel FinFETs structures come up constantly. In this brief, the impact of significant geometry parameters variations to device performance has been studied, such as fin height (H_fin), fin width (W_fin), fin spacing (S_fin), aspect ratio (W_fin/H_fin), and so on. In the result, we are able to determine the optimum device parameters for Multi-fin FinFETs. Meanwhile we analyze the parasitic gate capacitance and resistance of the multi-fin FinFETs using a conformal mapping method. To minimize the number of model fitting parameters, nondimensionalization technique is used. An effective lumped resistance model derived from distributed RC network is in use. Also, an analytical parasitic gate capacitance model is proposed, combined with parasitic capacitive couplings between source/drain fins and gates. Those analytical model can be applied for accurate circuit simulations of multi-fin FinFETs devices. The results presented in this paper can be of great help to device designers in designing 3-D devices as per their requirement.

Keywords

Optimized parameters device performance multi-fin FinFETs parasitic capacitance parasitic resistance conformal mapping

1 Introduction

Device with nonplanar gate structures such as FinFETs are one of the promising candidates for next generation devices because of their high immunity to short channel effects (SCEs), drain induced barrier lowering (DIBL), high gate controllability, and ideal subthreshold slope (SS) [1]. Most research work on multi-fin MOS devices have focused on their advantages in digital or switching applications [2]. Their performance for high frequency applications is not well studied. However, parasitic resistive [3] or capacitive components become comparable in magnitude to, or even much larger than, intrinsic ones [4]. In multi-fin FinFETs devices, parasitic have three primary components: 1) gate parasitic capacitances; 2) gate resistance; 3) source/drain (S/D) series resistance [5]. Gate parasitism are main factors in determining gate resistance-capacitance (RC) delay [6] and RF figure of merit (f_r = f_max) [7, 8]. Large series resistances [9], which are induced by the narrow-fin nature of nonplanar MOSFETs, result in a significant degradation of current drive in direct current operation regions. In addition, capacitive coupling with parasitic resistances even dominates device characteristics in analog/radio frequency (RF) integrated circuits (ICs) [10]. Moreover, conventional capacitance models cannot be applied directly to multi-fin FinFETs. It is necessary to establish a physical model associated with 3-D topography of SOI Multi-fin FinFETs.

This paper is organized in different sections. While Section 2 shows the device architecture of SOI Multi-fin FinFETs. Section 3 describes simulation methodology with validation of models in device simulator Sentaurus. Section 4 investigates the performance measure of the device for RF circuit applications with different Geometry Parameters. In Section 5, we derive a scalable gate-resistance model to compute the equivalent resistance with recursive algorithm. Meanwhile, in Section 6, we compose an analytic parasitic capacitance model for multi-fin FinFETs devices using conformal mapping method [11] and nondimensionalization technique. The final conclusions are drawn in Section 7.

2 Device design

Schematic diagrams and dimensions of a SOI multi-fin FinFETs with three fins are shown in Fig. 1. H_fin and W_fin are the fin height and width, respectively. S_fin denotes the fin spacing between two neighboring silicon fins. T_mask represents the hard mask thickness on top of a silicon fin. T_poly is the geometrical.

Fig.1

Schematic diagrams and dimensions of multi-fin FinFETs with three fins. (a) 3-D view. (b) Cross-section.

V_dLin = 50 mV and V_dSat = 0.9 V, Logarithmic leakage current thickness of gate material on top of the hard mask layer. T_ox is the thickness of the gate oxide. Gate length and source/drain extension length are defined as L_g and L_ext, respectively. The nominal device parameters are listed in Table 1. Form Fig. 2, it can be note that our simulation I_D - V_GS characteristics of multi-fin FinFETs.

Table 1

Nominal device parameters

Parameters	Description	Typical Value/nm
L _g	Gate length	14
H _fin	Fin height	20
W _fin	Fin width	8
T _mask	Hard mask thickness over fins	3
T _poly	Geometrical thickness of gate material over hard mask	7
S _fin	Fin spacing	10
T _ox	Thickness of gate oxide	0.8
L _ext	Source/Drain extension	10
G _wing	Length measured from the end of fin to the end of gate	10

Fig.2

I_D-V_GS characteristics of multi-fin FinFETs.

3 Imulation methodology

Modeling and simulation bridge the need for development and fabrication engineers by improving semiconductor process control in manufacturing. Sentaurus TCAD is a powerful GUI driven simulation environment for managing simulation tasks and analyzing results. Sentaurus TCAD simulations afford crucial insights on the nature of semiconductor devices, which can lead to new concepts. However, it needs to be properly calibrated for simulation.

Advantages of Sentaurus TCAD:

Reduces technology development time and cost.

Provides full flow 3-D process and device simulation with advanced structure generation, meshing, and numeric.

Supports insight into advanced physical phenomena, improving device design, yield, and reliability.

Provides fast prototyping, development and optimization of semiconductor technologies.

The technology parameters and the supply voltages used for the device simulations are according to the 2013 analog ITRS roadmap. The V_DD is taken as 0.9 V. The work functions of the polycrystalline silicon gates are adjusted to achieve the desired V_th values. The numerical simulation uses the drift-diffusion approach and the models activated in simulation comprise of field dependent mobility, concentration dependent mobility and velocity saturation model. The inversion layer mobility models Lombardi (constant voltage and temperature, CVT), and Auger recombination models are included [12].

The silicon bandgap narrowing model which determines the intrinsic carrier concentration is actuated. A set of partial differential equations for the modeled device solves self-consistently on the discrete mesh in an iterative fashion. The currents, voltages and charges for each electrode are calculated after each step of bias ramp through quasi-stationary. The Poisson equation, continuity equations, and the different thermal and energy equations are included in the simulation [13]. All the structure junctions are assumed as abrupt, the biasing conditions are reckoned at room temperature and the generation of smooth mesh is done in the simulation. The simulated results of FinFETs at low (50 mV) and high (0.9 V) drain biases are analyzed further.

4 Multi-fin FinFETs performance

Various performance metrics like V_th, I_off, g_m, I_d, subthreshold slope (SS) are evaluated and the sensitivity of above said parameters with W_fin, H_fin are systematically presented. Finally, depending upon the aspect ratio (W_fin/H_fin) of the device, the Sub-14 nm multi-fin FinFETs optimum parameters are determined.

4.1 Effect of H_fin

In this section, the sensitivity of H_fin with various key device parameters are studied. From the characteristic curve, i.e., I_D - V_GS, Some important technological parameters like V_th, I_off, g_m, SS and I_d are extracted for the device.

The sensitivity of V_th towards H_fin values is presented in Fig. 3. Threshold voltage for FinFETs is determined and controlled by the gate work function. However, it is very difficult to control V_th by tuning the gate work function in FinFETs because of integrative gate as shown in Fig. 1. So, here we have discussed about V_th control by adjusting the fin height. From Fig. 3, we can note that V_th decrease as H_fin increase ranging from 10.0 to 50.0 nm, leads to higher V_th roll-off. Owing to the threshold voltage is obtained in the case of two different drain voltages, it can also be noted that with the increasing of the drain voltage, the threshold voltage is significantly reduced. The more serious the drain voltage, the more severe the leakage of the source drain region into the channel region, which leads to weaken the thresholdvoltage.

Fig.3

threshold voltage (V_th) of device as a function of normalized Fin height (H_fin) for V_DS = 0.9 V and V_DS = 0.9 V.

Figure 4 shows the variation of subthreshold slope with V_DS at high (0.9 V) and low (50 mV) gate biases for different H_fin values. The subthreshold characteristic is defined as the current characteristic of the device when the gate voltage is less than the threshold voltage (i.e. V_GS < V_D). In general, the subthreshold characteristic is measured by the parameter subthreshold slope (SS). From Fig. 4, SS decreases with H_fin increases leads to optimization of the subthreshold characteristic and decreasing of subthreshold current. Also it can be noted that with the increasing of the drain voltage, the subthreshold slope (SS) is significantly raised and the subthreshold characteristic become more deteriorative.

Fig.4

subthreshold slope (SS) of device as a function of normalized Fin height (H_fin) for V_DS = 0.05 V and V_DS = 0.9 V.

Figure 5(a) and (b) show the plot of g_m and I_d for 14 nm FinFETs at high (0.9 V) and low (50 mV) drain biases for different H_fin values. To analyze the immense variety in g_m with an increase in H_fin values, we have evaluated and studied the I_D - H_fin and g_m - H_fin, respectively. According to the literature, access resistance problem is more serious in FinFETs. However, some solutions are available like increasing H_fin out of gate region [14]. The parasitic resistance problem can be avoided by using higher H_fin which further increases the drain current. This is also validated from Fig. 5(a) and (b), both the parameters, i.e., I_d and g_m are increasing with the increase in H_fin values.

Fig.5

(a) Transconductance (gm) of device as a function of normalized Fin height (H_fin) for V_DS = 0.05 V and V_DS = 0.9 V. (b) Drain current I_d of device as a function of normalized Fin height (H_fin) for V_DS = 0.05 V and V_DS = 0.9 V.

Figure 6 shows the extraction parameter from the characteristic curve like I_off at V_GS = V_DD. After analyzing Fig. 6, I_off is almost linearly increasing with increasing in H_fin.

Fig.6

I_off of device as a function of normalized Fin height (H_fin) for V_DS = 0.05 V and V_DS = 0.9 V.

Hence this is to highlight that device have higher current drivability with taller H_fin. Certainly, taller fins are required and for better SCE immunity, narrow fins are preferred. This is because narrow fins cause the decrease of electric filed in the silicon region which minimizes the leakage current.

By comparing the above parameters for all H_fin cases, we can say H_fin = 20nm or 25 nm are the optimum cases as they predict moderate values for both above parameters. Because at H_fin = 20 nm or 25 nm, maximum leakage current is obtained. Meanwhile device acquires appropriate V_th and SS which can better suppress short channel effect (SCE) and drain induced barrier lowering (DIBL). Also, minor I_off means that device can achieve higher gate controllability and more effective reduction of leakage current. Finally, not high fin can reduce the difficulty of the process for device fabrication.

4.2 Effect of W_fin

Similar type of analysis as in the previous section are systematically investigated and discussed with variation of W_fin values. By choosing a smaller W_fin, we can be able to minimize the longitudinal electric field at the source side because of closeness of multiple gates [15]. However, as scaling approaches the fundamental dimension such as atomic size range and the sensitivity of the device, parameters have a greater impact on the device performance. Particularly in case of analog/RF performance, the deviation of results is much larger with a small change in device design parameters. So in this paper we have systematically explored the impact of W_fin values on the RF performance of the FinFET.

The sensitivity of V_th towards W_fin values is presented in Fig. 7. The V_th is extracted from I_D - V_GS curve and plotted by varying W_fin values ranging from 3.0 to 15.0 nm. V_th decreases with an increase in W_fin values which further degrades the device performance because of the SCEs like DIBL and V_th roll-off. As W_fin decreases, the coupling between front and back interface is reduced which enhances V_th values. From this analogy, it may be predicted that by considering thicker H_fin and thinner W_fin we can enhance the FinFET performance. Figure 8 show the variation of subthreshold slope (SS) with V_DS at high (0.9 V) and low (50 mV) gate biases for different W_fin values. From Fig. 8, in horizontal comparison, SS increases with W_fin increases leads to deterioration of the subthreshold characteristic and increasing of subthreshold current. When the width of the fin is small, narrow channel can make the gate voltage better control channel. Furthermore, in vertical comparison, with the increasing of the drain voltage, the subthreshold slope (SS) is significantly raised and the subthreshold characteristic become more deteriorative.

Fig.7

threshold voltage (V_th) of device as a function of normalized Fin width (W_fin) for V_DS = 0.05 V and V_DS = 0.9 V.

Fig.8

subthreshold slope (SS) of device as a function of normalized Fin width (W_fin) for V_DS = 0.05 V and V_DS = 0.9 V.

Figure 9(a) and (b) show the g_m and I_d plot with a variation of W_fin at V_DS = 0.5 V and V_DS = 0.9 V respectively. Here W_fin is varied from 3.0 to 15.0 nm because for this foresaid technology node, Sun et al. [16] have reported that W_fin = 0.6 × L_g for FinFET is required to minimize SCEs. Both I_d and g_m are increasing with increase in W_fin values as predicted in picture. The effect of series resistance is clearly visible from Fig. 9(a) (low drain bias/linear region) by not following the linear dependency nature for low W_fin cases. From this analysis, we can say that the series resistance R_s is much higher for low Fin width devices.

Fig.9

(a) Transconductance (gm) of device as a function of normalized Fin width (W_fin) for V_DS = 0.05 V and V_DS = 0.9 V. (b) Drain current I_d of device as a function of normalized Fin width (W_fin) for V_DS = 0.05 V and V_DS = 0.9 V.

The extraction values of I_off are plotted against W_fin values in Fig. 10. As W_fin increased, I_off increases. And hence this is to highlight that device have higher current drivability with narrow W_fin. Here H_fin is fixed at 20 nm and W_fin is varied ranging from 3.0 to 15.0 nm. For W_fin = 8 nm, case we are getting desirable values for I_off.

Fig.10

I_off of device as a function of normalized Fin width (W_fin) for V_DS = 0.05 V and V_DS = 0.9 V.

By comparing the above parameters for all W_fin cases, we can say W_fin = 8 nm are the optimum cases as they predict moderate values for both above parameters. Because at W_fin = 8 nm, we can obtain relatively large drain current. Meanwhile narrow fin device can acquire appropriate V_th and SS which can better suppress short channel effect (SCE) and drain induced barrier lowering (DIBL). Also, minor I_off means that device can achieve higher gate controllability and more effective reduction of leakage current. Finally, not too narrow fin can reduce the difficulty of the process for device fabrication.

Up to this, we have systematically investigated the parameter variation (W_fin and H_fin) effects on various device performances. From the above study, taller fins are needed for higher current drivability and also shows a little improvement in highly frequency of operation whereas shorter fins are required for better SCEs. From this point of view, aspect ratio (AR = W_fin/H_fin) of the device is a very interesting and important parameter from FinFET design consideration point of view. In this paper, we consider AR = 0.4 is more appropriate choose.

5 Parasitic resistance modeling

For conventional CMOS devices, distributed gate RC delay has been researched with infinitesimally small RC components. Due to the three dimensional nature of the FinFET, the gate RC distributed effects is more complex. Therefore, we present a scalable gate resistance model to account for the effect of gate resistance of multi-fin FinFETs devices. Figure 11 shows the resistive values of the equivalent RC network with effective lumped components [17].

Fig.11

RC network with effective lumped components. The equivalent gate resistances between n-fin and (n-1)-fin structure is represented.

It reveals the recursive relationship of equivalent gate resistances between n-fin and (n-1)-fin FinFET structure. the expressions of R₁, R₂ and R_c are as follows: $R_{C} = \frac{2 ρ H_{fin}}{3 S_{fin}}$ (1) $R_{1} = k_{1} (S_{fin} + 2 T_{OX} + W_{fin}) / T_{poly}$ (2) $R_{2} = k_{2} (T_{poly} / 2 + T_{mask}) / S_{fin}$ (3)

Where ρ is the sheet resistivity of gate materials, and k₁ and k₂ are two fitting geometry independent parameters account for process dependent variables such as polysilicon resistivity, corner effects and spreading effects. They can be obtained from 2-D MEDICI simulation, and they are equal to 1.2 and 0.7, respectively [5]. R_C is a lumped resistor represents the distributed part of R_g and C_g is the corresponding capacitance for every channel. We admit equivalent resistance R_eq and capacitance C_eq can indicate gate RC delays of multi-fin FinFETs structures. Base on (1) (2) (3), we can obtain the recurrence formula for the equivalent resistors.

$\begin{matrix} R_{eq, n} & = & \frac{R_{2} + R_{C} / 2}{2 (n + 1)^{2}} + \frac{n^{2} (R_{eq, n - 1} + R_{1})}{(n + 1)^{2}} \\ = & \frac{(n - 1) (R_{2} + \frac{R_{C}}{2})}{2 n^{2}} + \frac{(n + 1) (2 n + 1) R_{1}}{6 n} \\ + R_{eq, 1} \end{matrix}$ (4)

It has been proved that the determination of geometrical parameters (e.g., H_fin, W_fin, S_fin, T_mask and etc.) would make a great difference in device performance. S_fin is the primary parameter for the gate resistance of multi-fin FinFETs. Considering the circuit layout density, S_fin had better not more than twice for H_fin. And optimal fin spacing S_opt can be proposed based on the model above, to determine the minimal R_eq. $S_{opt} = \sqrt{\frac{3 (n - 1) T_{poly} (\frac{k_{2} T_{poly}}{2} + k_{2} T_{mask} + \frac{ρ H_{fin}}{3})}{n (n + 1) (2 n + 1) k_{1}}}$ (5)

Base on (4) and (6) we obtain the expression of minimal equivalent gate resistance as

$\begin{matrix} R_{eq, min} (n) & = & \sqrt{\frac{(n^{2} - 1) (2 n + 1) [k_{1} k_{2} (T_{poly} / 2 + T_{mask}) + k_{1} ρ H_{fin} / 3]}{3 n^{3} L_{g}^{2} T_{poly}}} \\ + \frac{(n + 1) (2 n + 1) k_{1} (2 T_{OX} + W_{fin})}{6 {nT}_{poly} L_{g}} + R_{eq, 1} \end{matrix}$ (6)

For different gate materials, S_opt has different values. For example, when we use the metal gate, the value of S_opt is usually smaller. When S_fin exceeding S_opt, gate resistance rapid increase with increasing of S_fin. Hence It have a great influence on RF/analogy performance of devices.

6 Parasitic capacitance modeling

In multi-fin FinFETs device, parasitic capacitances C_p consist of the fringing capacitance C_fr and the overlap capacitance C_ov. C_ov in multi-fin FinFETs can be modeled using a conventional MOSFET method [5] which can be expressed as

$C_{ov} = n (2 W_{fin} * c_{ov} (T_{mask}) + 4 H_{fin} * c_{ov} (T_{OX}))$ (7)

Where

$\begin{matrix} c_{ov} (t) & = & \frac{ɛ_{OX}}{2} [1 + \frac{1 - cos (\frac{π}{2} \frac{ɛ_{OX}}{ɛ_{Si}})}{sin (\frac{π}{2} \frac{ɛ_{OX}}{ɛ_{Si}})}] + \frac{L_{ov}}{t} ɛ_{OX} \\ + \frac{2 ɛ_{Si}}{π} ln [1 + \frac{x_{j}}{t} sin (\frac{ɛ_{OX}}{ɛ_{Si}})] \end{matrix}$ (8)

And X_j is the junction depth, L_ov is the length of S/D region overlapping the gate electrode which is preferred to be small. In addition, X_j would be W_fin/2 in this case. The fringing capacitance C_fr contains two parts: inner part C_if and outer part C_of. However, C_if has been proved to be almost zero due to a strong inversion. Hence, in this paper, we only derive the analytical model of outer fringing capacitance of multi-fin FinFETs. Due to complex coupling effect of 3-D architecture, we decompose C_of into several parts to simplify the analysis.

In Fig. 12(a), C₁ represents the electric flux from top of polysilicon gate electrode to the top of silicon fins, and C₂ is associated with the electric flux from the gate sidewall to the top surfaces of silicon fins. From the Fig. 12(b), C₃ is defined to the electric flux from the sidewall of the fin to the sidewall of gate at the edge area. C₄ has the similar definition with C₃, however it need to be calculated differently because of source/drain pad connecting the fins. Obviously, C₅ represents the electric flux between the sidewall of source/drain pad and gate electrode. In addition, there are also some other components of parasitism, like the electric flux from the sidewall of gate to the end of source/drain pad and the electric flux from the end of gate to the sidewall of the fin at edge area. However, it has been proved their contribution is less than 5%, and they are neglected for simplicity in this case.

Fig.12

Notation of outer fringing capacitances of multi-fin (n = 3) FinFET architecture.

As done in some previous works [18], C₁ and C₂ were calculated as $C_{1} = \frac{ɛ_{OX} (W_{fin} + S_{fin} + 2 T_{OX})}{π} ln (1 + \frac{L_{g}}{1 + T_{poly} + T_{mask}})$ (9) $\begin{matrix} C_{2} & = & \frac{ɛ_{OX} W_{fin}}{π} ln (\frac{T_{mask} + η_{1} T_{poly} + \sqrt{(η_{1} T_{poly})^{2} + 2 η_{1} T_{mask} T_{poly}}}{T_{mask}}) \\ + \frac{η_{2} ɛ_{OX} W_{fin} e^{- 1}}{π} ln \frac{π W_{fin}}{T_{mask}} \end{matrix}$ (10) Where $η_{1} = exp (\frac{L_{ext} - \sqrt{T_{poly}^{2} + 2 T_{mask} T_{poly}}}{τ_{1} L_{ext}})$ (11)

The two geometry-independent parameters η₂ and τ₁ are determined to fit the Raphal simulation results, and they are found to be 7.9 and 15,respectively.

C₃ and C₄ have the same formulation, but the values of parameters are different [19]

$\begin{matrix} C_{3, 4} & = & \frac{ɛ_{OX} H_{fin}}{π} ln [\frac{T_{OX} + η_{3, 4} W_{3, 4} + \sqrt{(η_{3, 4} W_{3, 4})^{2} + 2 T_{OX} η_{3} W_{3, 4}}}{T_{OX}}] \\ + \frac{ɛ_{OX} H_{fin} e^{- 1}}{π} ln \frac{2 π H_{fin}}{T_{OX}} k_{3, 4} ∥ \end{matrix}$ (12)

Where

$η_{3, 4} = τ_{3, 4} exp {σ_{3, 4} {[1 - \sqrt{{(\frac{W_{3, 4} + T_{OX}}{L_{ext}})}^{2} - {(\frac{T_{OX}}{L_{ext}})}^{2}}]}^{2}}$ (13)

For C₃, W₃ is G_wing. Which represents the gate extension length measured from the end of fin side to the end of gate. The parameters of τ₃, σ₃, k₃ are 1.272, 0.87, and 2.635, respectively. For C₄, W₄ is S_fin/2, and τ₄, σ₄, k₄ are 1.005, 0.63, and 2.339, respectively. $C_{5} = \frac{ɛ_{OX} H_{fin} S_{fin}}{L_{ext}} [\frac{τ_{5} (S_{fin} + 2 T_{OX})}{L_{ext}} + k_{5}]$ (14)

Where the values of k₅ and τ₇ are 0.060 and 3.357, respectively.

Consequently, the total fringing capacitance in the n-fins FinFET architecture are formulated as follows:

$\begin{matrix} C_{fr} & = & 2 n (C_{1} + C_{2}) + 4 C_{3} \\ + 4 (n - 1) C_{4} + 2 (n - 1) C_{5} \end{matrix}$ (15)

From the above results, the total gate parasitic capacitance is calculated as follows: $C_{p} = C_{fr} + C_{ov}$ (16)

Figure 13(a) shows the relation about C₃ with the G_wing and C₄ with the S_fin from the proposed analytical models, and it reveals C₃ and C₄ increase linearly to G_wing and S_fin. The simulation result of C₅ as a function of S_fin is shown in Fig. 13(b). Also, it can be note that C₅ increase linearly to S_fin.

Fig.13

(a) C₃ versus G_wing and C₄ versus S_fin. (b) C₅ versus S_fin.

Figure 14(a) and (b) give an obvious description on C₃, C₄ and C₅ versus L_ext. C₃ and C₄ decrease firstly with the increasing L_ext and then increase when L_ext exceeds 10 nm. Also, C₅ decreases sharply to L_ext, and becomes steady until L_ext over 12 nm. Therefore, the optimization of L_ext should be investigated in details depending on practice. In addition, C₅ is proved to be the most dominant term among the fringing capacitive components. However, it is worth noting that oversize L_ext leads to increase equivalent gate length, and affect device performance.

Fig.14

(a) C₃ or C₄ versus L_ext. (b) C₅ versus L_ext.

Figure 15 exhibits total fringing capacitance C_fr of multi-fin FinFETs versus different S_fin and the number of fins N_fin when L_ext equals 10 nm. It reveals that C_fr keeps increasing with the increase of L_ext and N_fin. For formula (16), C_ov can be regarded as a constant. Therefore, the total gate parasitic capacitance increases as well when L_ext and N_finincrease.

Fig.15

Total fringing capacitance versus N_fin with various S_fin.

7 Conclusion

In this paper, the process parameters like H_fin, W_fin and Aspect Ratio (AR = W_fin/H_fin) are most important for designing FinFETs. This report provides an extensive analysis of process variability parameters in device design perspective point of view. From the results, it is deduced that taller fins are required for higher current drivability and narrower fins are required for higher immunization to SCEs. In case of H_fin variation, H_fin = 20 nm shows the optimum device performances in terms of gain, transconductance and maximum drain current. By thinning the W_fin, FinFET can be freed from substrate related effects which further improves the gain and R₀ of the device. Meanwhile, practical models for parasitic resistance and capacitances of multi-fin FinFETs are proposed. The expression of minimal equivalent gate resistance is derived with the optimal fin spacing. Then, it is found that the geometry parameters such as G_wing, S_fin, L_ext and N_fin have a great influence on parasitic capacitance. The proposed analytical model can be implemented for device optimization of multi-fin FinFETs architecture. Thus, this paper provides valuable results to design a multi-fin FinFETs according to the requirement for high performance or low standby power applications. Furthermore, the impact of key geometric parameters on circuit performance will be considered by realizing a CMOS inverter and an SRAMs circuit.

Footnotes

Acknowledgments

This work was supported by project of 14 nm technology generation silicon-based novel devices and key crafts research (2015AA016501) and CSC.

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