A Fuzzy controlled high gain DC–DC converter for renewable power generation

Abstract

In this manuscript a DC non-isolated converter model with high static voltage gain module is presented. The proposed converter has the feature of stable frequency and stable output voltage. It also achieves high voltage conversion, high efficiency, low voltage stress and less switching loss. The voltage tripler technique is implemented in the proposed model. The designed converter model attains high static gain with reduced duty cycle. The proposed single switch converter is controlled by fuzzy-PI controlled technique. The working process of the converter under Continuous Conduction Mode (CCM) is explained. The 30 V input source is boosted up to 400 V. The simulation of the presented converter is done with MATLAB simulink. The hardware prototype is also tested and results are analysed.

Keywords

Continuous conduction mode duty-cycle high voltage gain fuzzy-PI voltage tripler

1 Introduction

Due to the increase in demand in conventional sources there is an increase in renewable energy generation. They have an advantage such as abundant in nature, free from pollution and sustainable. The sources of renewable energy production occurs from solar, wind, hydro, tidal and bioenergy. Among them solar and wind plays a major production in power generation. Since they avail all time source and has a better efficiency compared to other sources. Nowadays many researchers show their interest in solar and wind to improve their production and to make it avail even in all parts of the world [1].

The output power of solar or wind attained is in the level of 12–48 V. So to boost up the voltage and to balance to grid and load voltage boost converters plays a major role. These power converters are extensively used to increase the voltage range from 24 V to 220 V or more than it. But it was not that easy to attain the high voltage gain, since the voltage ratios to be matched many level of converters has been developed [2].

In tradition boost type converter it was hard to attain the aimed voltage gain due to problems such as diode reverse retrieval tricky and switch strain at high duty range. So cascaded mode boost converter has been developed to attain high gain but it results in reduction of efficiency due to increase in components [3, 4]. As next step magnetically coupled converter model such as fly-back converter, push-pull model and full bridge type came to usage to deliver the attained voltage ratio by carefully selecting turns proportion of transformer. Tactlessly, the seepage energy in inductance occurs in magnetic properties which results in extra voltage strain and component loss [5, 6]. Hence the next research stepped in the absence of transformer models. To enrich the voltage gain in absence of transformer comprises Voltage Multiplier Cell (VMC), Coupled Inductor (CI) and Switched Capacitor (SC) networks [7 –9]. The range of voltage gain is attained by VMC model but their power management ability is restricted by their module count [10, 11].

To boost voltage many converters has been developed such as Sepic, Cuk, Luo etc … The voltage gain achieved in those converters were more compared to traditional converter with improved efficiency level. In order to improve the range these converters were also combined with VMC, CI, SC and voltage lift techniques [7 –9]. In this manuscript a new converter has been proposed. This converter is of modified Sepic model with Voltage Tripler (VT) mode integrated design. This converter reaches extreme voltage gain with improved effectiveness and decreased switching losses, reduced capacitor and inductor ripples.

Controllers perform a main role in the converter working. Many traditional checkers such as Proportional (P), Proportional-Integral (PI), and Proportional-Integral-Derivative (PID) have been in use. In trending artificial networks system shows a vigorous role in controlling the converter. Among them fuzzy logic is extensively utilized in DC converter and it is also utilized in the combination of fuzzy with PI [13], fuzzy with sliding mode etc. [14]. Fuzzy controllers are also combined with Perturb and Observation (P&O) method of MPPT tracking for solar photovoltaic [15 –17]. These fuzzy controllers are also utilized in grid side for controlling voltage frequency in the microgrid for islanding operation [18 –20].

This paper projects a proposed DC–DC modified Sepic converter model which is utilized to attain a high voltage gain conversion with good efficiency and reduced voltage, current ripples and switching losses. In section 2 the designed converter working is clarified. In section 3 the analytical part of the design is discussed. The section 4 is followed with fuzzy control technique. In section 5 the evaluation of the presented converter with multilevel Sepic converter is discussed. Simulation and hardware examination is clarified in section 6. Then conclusion part is followed by section 7.

2 Operating principle of the proposed converter

The designed model is represented in Fig. 1.The design consists of key switch S₁, inductors L₁, L₂, diodes D₁, D₂, D₃, D₄, D₅, D₀ and capacitors C₁, C₂, C₃, C₄, C₅, C₀. The VT is united with non-isolated Sepic converter to increase the static voltage ratio of the converter. The voltage across switch in the semiconductor device is reduced. Capacitors operate as similar operation in conventional boost converter. The model here works in CCM and it works under the condition when switch turns ON and OFF. The modes of operation are presented below.

Fig. 1

Proposed single switch DC–DC converter.

2.1 Continuous conduction mode operation

The proposed model works in dual modes. The modes of operations are shown in Figs. 2 and 3.

Fig. 2

Proposed DC–DC converters turn ON mode.

Fig. 3

Proposed DC–DC converters turn OFF mode.

Mode I [t0–t1]: As the switch S₁ is switched ON; diodes D₂, D₄, and D₀ are turned ON. Diode D₁, D₃ and D₅ are reverse biased. The voltage V_in is delivered to L₁ and V_{C
₃} - V_{C
₂} - V_{C
₁} is delivered to L₂. These inductors help in storing the energy.

The capacitor C₀ ejects the energy required to the operating load for its operation. With the switch OFF, this mode ends. Also, the current in diode D₁ and D₃ attain zero at t = t₁.

Mode II [t1–t2]: With the switch S₁ turned OFF, the diodes D₂ and D₄ are in Reverse condition. The diodes D₁, D₃ and D₅ are in ON state. The inductors L₁ and L₂ charge the capacitors. The load receives the energy by discharging mode of the capacitor. This operation cedes with the switch turned ON. This continues to the next cycle. The main operational waveform is represented in Fig. 4. The total capacitive voltage equals the output voltage of the converter.

Fig. 4

CCM operation waveforms.

$V_{C_{0}} = V_{C_{3}} + V_{C_{4}} + V_{C_{5}}$ (1)

3 Design analysis of the proposed converter

On the basis of the analytical expression of the converter operation, the component design values are selected.

3.1 Duty cycle calculation

In designed converters voltage varies owing to the duty cycle control. And also it is dependent on elements in the circuit. The output of the presented converter is specified as, $\underset{0}{V} = \frac{D \times 3 \underset{in}{V}}{1 - D}$ (2)

On taking the diode voltage drop in to account, $\underset{0}{V} + \underset{d}{V} = \frac{D \times 3 \underset{in}{V}}{1 - D}$ (3)

On simplifying, $D = \frac{\underset{0}{V} - 3 \underset{in}{V} + \underset{d}{V}}{\underset{0}{V} + 3 \underset{in}{V} + \underset{d}{V}}$ (4)

On substituting the values, we get $D = \frac{400 - 90 + 0.7}{400 + 90 + 0.7} = 0.77$

The attained duty cycle is 0.77.

Here V_d = Diode drop voltage

V₀ = Output voltage

V_in = Input voltage

3.2 Inductor selection

The inductance values are identified with the help of input current ripples. i.e. ΔI_{L
₁} and ΔI_{L
₂}. The values of the input current ripples are 1.77 A. The switching voltage and static gain is depicted in Figs. 5 and 6. The voltage static gain is 11 and its high for the designed converter compared to other type. Also the witching voltage for the proposed converter is less compared to other converters. Since the switching voltage is less, the strain on the switch is less which reduces loss and improves efficiency.

Fig. 5

Voltage gain analysis.

Fig. 6

Switching voltage of proposed converter.

$\underset{1}{L} = \frac{D \times 3 \underset{in}{V}}{f \times \underset{L 1}{Δ I}}$ (5) $\underset{2}{L} = \frac{(1 - D) \times \underset{C 2}{V}}{f \times \underset{L 2}{Δ I}}$ (6) $\underset{ripple}{I} = \underset{out}{I} \times \frac{\underset{out}{V}}{\underset{in}{3 V}} \times 40 %$ (7) $Where \underset{1}{L} = \frac{0.77 \times 3 \times 30}{24000 \times 1.161} = 146.7 μ H$ $\underset{2}{L} = \frac{(1 - 0.77) \times 154.7}{24000 \times 1.16} = 205 μ H$

3.3 Capacitor selection

Voltage ripple (Δv_c) is used to calculate the capacitance value. The ripple value is obtained by the 10% of the input voltage value. The capacitive ripple current is obtained using Equation 9 and the ripple voltage is 0.104 V. The formula to obtain the capacitor value is given by, $\underset{1}{C} = \underset{2}{C} = \underset{3}{C} = \frac{\underset{0}{I}}{f \times \underset{C}{Δ V}}$ (8) $\underset{1}{C} = \underset{2}{C} = \underset{3}{C} = \frac{0.9}{24000 \times 1.77} = 2.2 μ F$

The ripple voltage is obtained by, $\underset{C}{Δ V} = \frac{\underset{o}{I}}{\underset{o}{C} f}$ (9) $\underset{C}{Δ V} = \frac{0.9}{398 \times 24000} = 1.77 V$

The ripple capacitive current is attained by, $\underset{CS}{I} = \underset{0}{I} \times \sqrt{\frac{\underset{0}{V}}{3 \underset{in}{V}}}$ (10) $\underset{CS}{I} = 0.9 \times \sqrt{\frac{390}{90}} = 1.8 A$

3.4 Output capacitor

The capacitor c₀ is calculated as same as boost converter design. To calculate the output capacitor frequency (f_c), output power (p₀), output voltage (V₀) and output ripple voltage (ΔV) ₀. 1% of output voltage is identical to V₀ ripple voltage. The capacitance is calculated using $\underset{0}{C} = \frac{\underset{0}{p}}{4 π \underset{g}{f} \underset{0}{V} \underset{C}{Δ V}}$ (11) $\underset{0}{C} = \frac{400}{4 \times Π \times 24000 \times 400 \times 1.77} = 40 μ F$

3.5 Component stress

The component design purpose for the current across switch is i₁ and i₂ during turn ON and end of turn ON is found using below equation. On taking the theoretical efficiency value is 97.3%. The efficiency depends on load utilized. Here the RMS current of the switch (i_rms) $\underset{1}{i} = (\frac{\underset{0}{p}}{η * \underset{in}{V}} - \frac{\underset{L}{Δ I}}{2}) + (\underset{0}{i} - \frac{\underset{L}{Δ I}}{2}) = 0.185 A$ (12) $\underset{2}{i} = (\frac{\underset{0}{p}}{η * \underset{in}{V}} + \frac{\underset{L}{Δ I}}{2}) + (\underset{0}{i} + \frac{\underset{L}{Δ I}}{2}) = 1.67 A$ (13) $\underset{rms}{i} = (\sqrt{\frac{1}{3} • (i_{1}^{2} + i_{2}^{2} + \underset{1 •}{i} \underset{2}{i})}) . d = 0.44 A$ (14)

The output current (i₀) is same as diode current i_{D
₁}, i_{D
₂} and i_{D
₀} $\underset{0}{i} = \underset{D 1}{i} = \frac{\underset{0}{p}}{\underset{0}{V}}$ (15) $\underset{0}{i} = \frac{400}{400} = 1 A$

4 Control technique of the designed converter

Here the projected converter exploits Fuzzy-PI control techniques. Fuzzy Logic Controller (FLC) is best booming solicitations of fuzzy concept, implemented by Zadeh in 1965]. Its best structures are the usage of language variables relatively than numerical contents. Linguistic variables are utilized as normal variables are such as minor and great, which is characterized as fuzzy sets. It is an addition of a crisp set which exhibits the membership or non-member ship function. Fuzzy sets permits specific function which defines that an element may belong or may not belong to the set. The main concept of fuzzy is the rules. The rules should be defined first according to the converter operation. Here in this design, the error and modification in error is assumed as input to the fuzzy converter. The change in error is created by delay unit. The output of the fuzzy controller is compared with relational operator and it is given to the gate of the MOSFET.

FLC entails of three main blocks specifically fuzzification, FIS and defuzzification. In fuzzification the data is converted to linguistic variable. Totally two fuzzification approaches they are, Mamdani and Sugeno. Scheme of membership function for input error, input change in error and output duty is shown in Fig. 7. To attain crunchy output diverse defuzzification systems can be utilized e.g., centre of gravity. Rule base and data base are given to decision making. The converter rules for fuzzy controller is depicted in Fig. 8 and surface plot is represented in Fig. 9.

Fig. 7

a) Error, b) Change in error, c) duty cycle member ship functions.

Fig. 8

Fuzzy controller rules.

Fig. 9

Surface plot of fuzzy.

4.1 Fuzzy-PI controller

Fuzzy logic makes a combination with conventional PI controller. Error and modification in error is specified as input to the FLC and incremental change of controller sign is the output of the fuzzy system. The error and modification in error is specified as below $Error : e = v_{0} - v_{ref}$ (16) $Change in error : c_{e} = e_{k} - e_{k - 1}$ (17) The rules of FLC are described below.

IF the V₀ of the model is far-off from the V_ref point, the inflection of the duty range needs to be great to fetch the end point rapidly.

IF the V₀ of the model is impending the end pt., a minor inflection of duty range is essential

IF the V₀ of the model is close the end point AND is imminent it quickly, the duty range should be retained continuous to avert overrun

IF the end point is stretched AND the V₀ still wavering, the duty range need to be altered a slight bit to avert the V₀ since stirring away

IF the end point is stretched AND the V₀ is stable, the duty range remnants unaffected.

IF the V₀ is overhead the set opinion, the indication of the alteration of the duty cycle need to be negative, and vice-versa.

The control structure of fuzzy is revealed below in Fig. 10. The V₀ and V_ref voltage is analysed to get the error value and then the delay circuit is given to optimize the modification in error value. The error (ref voltage) and modification in error (error voltage) is specified as input to the fuzzy controller and the change in control is taken as output which is fed to switch as gating pulse.

Fig. 10

Fuzzy-PI controller for proposed converter.

5 Results and analysis

5.1 Simulation results

In proposed converter output voltage ripple level is much small and the steady state is attained at earliest. The maximum over shoot is 0% and the transient response analysis is better than multilevel sepic converter. The output voltage is reliable and hence switching operation is good with reduced conduction loss and switching loss. The inductive voltage occurs only in positive value. From the Fig. 11, the output voltage attained from proposed converter is less in ripple, the maximum over shoot is 0%, the settling time is 0.5 ms and the steady state error is 0.6%. This output signifies that the converter operates in stable state. The ripple in the output voltage is less which provides the best performance of the presented converter model.

Fig. 11

Simulation results of the proposed converter. a) output voltage, b) output current, c) inductive current and d) capacitive voltage).

5.2 Hardware analysis

The Proposed converter is verified under the laboratory prototype and the outcomes obtained are same as simulation results. The input voltage source of 30 V is obtained from regulated power supply. The dspace 1104 model controller is utilized to generate switching pulse for MOSFET switch. The duty cycle is engendered by utilizing the switching frequency limit of 24 kHz.

The real-time outcomes acquired are exposed in Figs. 12–15. In Fig. 12 the voltage V₀ and output current results are depicted. Also the transient analysis of the converter under closed loop is depicted with hardware results. In Fig. 13 the capacitive voltage, gate and drain voltage is depicted. The ripple current and voltage is less compared to other converters and it is tested with hardware and results are depicted in Fig. 14. Hardware prototype is revealed in Fig. 16. The duty control range of the converter is 19.38% and it is verified from the above result. Also from the above result it is depicted that the attained efficacy of the designed converter is 97.3%. Hence the efficiency is proved by both theoretical and hardware analysis. And also the ripple voltage and current are less compared to other converter and it is proven with hardware results.

Fig. 12

Hardware results of proposed converter (voltage and current) and steady state response.

Fig. 13

Hardware results of a) capacitive voltage, b) gate source and c) drain source.

Fig. 14

Ripple voltage and ripple current of the proposed converter.

Fig. 15

Hardware setup of the proposed converter.

Fig. 16

Multilevel sepic converter.

6 Comparative analysis

The presented model is associated with the multilevel sepic converter. On comparing the output of the presented design and the multilevel converter, the output voltage is not stable and it has more ripples compared to the proposed converter. The Fig. 16 depicts the simulation results of the multilevel sepic. The transient response analysis is compared and it is depicted in Table 1.

Table 1
Transient response analysis

Transient response Multilevel sepic converter Proposed converter

Settling time 0.5 ms 0.15 ms

Peak time 0.08 ms 0.03 ms

Rise time 0.06 ms 0.014 ms

Maximum overshoot 5% 0.1%

Steady state error 1.6% 0.25 or 0.6%

Transient response	Multilevel sepic converter	Proposed converter
Settling time	0.5 ms	0.15 ms
Peak time	0.08 ms	0.03 ms
Rise time	0.06 ms	0.014 ms
Maximum overshoot	5%	0.1%
Steady state error	1.6%	0.25 or 0.6%

From the above Table 1 it’s seen that the proposed converter has good transient response compared to the multilevel sepic non isolated converter. The transient analysis is checked with hardware prototype. Since the proposed converter has good transient response the efficiency is increased with high voltage gain and the losses are reduced. The Parameter evaluation is depicted in Table 2.

Table 2

Parameter comparison

Components	Sepic	Modified Sepic	Multilevel sepic boost	Proposed converter
Input voltage Vin	30 V	30 V	30 V	30 V
Switching frequency (f)	24 kHz	24 kHz	24 kH	24 kHz
Duty Cycle(D)	0.91	0.82	0.82	0.77
L₁, L₂	L1 = 112.5μH	113.75μH	102μH	200μH
C₁, C₂, C₃, C₄,	2.2μF	1.518μF	50μF	2.2μF
C₀	100μF	100μF	3.37μF	20μF
R	224.88 Ω	224.8 Ω	224.88 Ω	400 Ω

Table 3

Performance comparison of the proposed converter

Components	Sepic	Modified sepic	Modified sepic boost	Proposed converter
Output Voltage (V)	147.5 V	150 V	150 V	400 V
Input voltage (V)	30 V	30 V	30 V	30 V
Switch voltage (Vs)	162.3 V	83.8 V	81.3 V	200 V
Inductor current (I_in)	76 A	70 A	54.5 A	15 A
Output current (I_out)	0.6572 A	0.6715 A	0.6699 A	0.9 A
Output power (P_out)	97 W	100 W	100 W	400 W
Ripple current	2.5 A	2.5 A	2 A	0.5 A
Ripple voltage	6 V	4 V	4 V	2 V

Also the enactment comparison of the designed converter with conservative converter is depicted in Table 3. According to the contrast of the below table, the input current to the power converter is a smaller amount, which diminishes the inrush current limit and develops the efficiency. Also the presented converter attains high static gain with compact ripple current and voltage. The output ripple voltage is 2 V and ripple current is 0.5 A.

The evaluation of efficacy among the proposed converter and the multilevel sepic converter is depicted in the Fig. 17. And its proved that the proposed converter has a good efficiency and the efficiency attained is proved with the experimental results.The experimental hardware efficiency result of the designed converter is depicted in the Fig. 18.

Fig. 18

Hardware result of efficiency plot.

Fig. 17

Efficiency comparison.

7 Conclusion

In this manuscript high voltage gain modified multilevel sepic converter has been proposed. The working and operation of the designed converter in CCM mode is explained. The operation of the converter is detailed by the waveform depiction. The proposed model attains high static gain with reduce switching and conduction loss. The concept of VT has been embedded to improve the boosting of voltage ratio with efficiency. The steady state and design analysis has been explained. The simulation investigation of the designed converter is presented clearly on comparing with multilevel sepic converter results. The transient response analysis of the designed converter is explained. A hardware prototype has been developed in laboratory and proved the working of converter. The investigational outcomes prove that the designed converter attains high stepping of voltage with tripling of voltage level with an efficiency of 94% with reduced switching stress.

Footnotes

Acknowledgment

The authors would like to thank Vellore Institute of Technology, Vellore for providing ‘VIT SEED GRANT’ for carrying out this research work.

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A Fuzzy controlled high gain DC–DC converter for renewable power generation

Abstract

Keywords

1 Introduction

2 Operating principle of the proposed converter

3.1 Duty cycle calculation

5.1 Simulation results

Table 1 Transient response analysis Transient response Multilevel sepic converter Proposed converter Settling time 0.5 ms 0.15 ms Peak time 0.08 ms 0.03 ms Rise time 0.06 ms 0.014 ms Maximum overshoot 5% 0.1% Steady state error 1.6% 0.25 or 0.6%

Footnotes

Acknowledgment

References

Table 1
Transient response analysis

Transient response Multilevel sepic converter Proposed converter

Settling time 0.5 ms 0.15 ms

Peak time 0.08 ms 0.03 ms

Rise time 0.06 ms 0.014 ms

Maximum overshoot 5% 0.1%

Steady state error 1.6% 0.25 or 0.6%