Optimization and control of CMOS analog integrated circuits for cyber-physical systems using hybrid grey wolf optimization algorithm

Abstract

Guaranteeing the reliability of cyber-physical systems (CPS) requires analog integrated circuits for correct functioning. Analog integrated circuits capture the continuous signal and amplify the signal for further processing in CPS applications. This paper presents the hybrid swarm intelligence based approach for determining the optimal transistors sizes and bias current values of CMOS differential amplifier and an operational amplifier. We proposed the simplex search based global optimization method called a hybrid grey wolf optimization (GWO) for solving amplifiers circuit sizing problems. Simplex and GWO techniques were combined to improve the local search capabilities of the optimization method. Our main aim is to optimize the transistor size and bias current values using hybrid GWO algorithm for an optimal design of the CMOS amplifiers. CMOS 180 nm technology was utilized to finding the circuit performance using proposed optimization approach. Simulation result shows that the proposed method provides the better result for circuit performance parameters such as DC gain, phase margin, unity gain bandwidth and power dissipation.

Keywords

Cyber-physical systems CMOS amplifiers circuit design optimization grey wolf optimization simplex method circuit sizing

1 Introduction

Cyber- physical systems (CPS) is a combination of computers and physical systems [1]. The CPS receives the continuous signal from the physical system and computer used to monitor these signals. The general structure of CPS architecture is shown in Fig. 1. Cyber and physical components closely interact to the physical surroundings with the help of the software and mixed-signal (analog and digital) hardware systems. Currently, CPS amplifications are ranging from automotive systems to medical devices, such as autonomous vehicle system, security systems, autonomous robotics and health-care components. Time to market and security of CPS applications are the important constraints for the design of CPS. Time to market and security of CPS applications are the important constraints for the design of CPS.

Fig.1

Structure of Cyber-physical systems components.

Design of cyber-physical systems (CPS) is a complex one mainly because of the real world communication, such as continuous signal which can be amplified by the analog circuits. A single CPS consists of more than 100 integrated circuits (ICs) for specific applications. Time to market and security of CPS applications are the important constraints for the design of CPS. Design of cyber-physical systems (CPS) is a complex one mainly because of the real world communication, such as continuous signal which can be amplified by the analog circuits. A single CPS consists of more than 100 integrated circuits (ICs) for specific applications.

For real-world CPS applications, the analog block is one of the key parts to design a VLSI system. Although the analog circuits occupy a little parts of integrated circuits (ICs) and its application towards the real world communication is a crucial one. The integration and implementation of mixed-signal ICs consist of digital parts analog parts. System on chip technologies combines the analog and digital parts in a single chip with the same device technology. There are so many design automation tools available for the design of digital circuits with accurate results. In case of analog circuits, the design is a challenging process because of its nonlinear behavior. So the analog circuits design needs a highly skilled analog designer to complicating the trade-off between design specifications, variables, and constraints. Hence the design of the analog circuit requires huge time for optimal results [2]. Over the last two decades, the researchers proposed so many design methods for analog circuits [3]. This kind of design is also called as electronic design automation or analog design automation [4].

The analog design parts can be classified into three types of design categories:

Topology selection

Transistor sizing

Layout generation

In circuit topologies selection, circuits are selected depend on the user specification for system design. A complete system consists of many simple and complex circuits. The circuit sizing step a designer need to specify the optimal transistor sizes and input parameter values based on the circuit specifications. Finally, these circuits are converted into a layout for chip manufacturing. This work mainly focuses on transistor sizing because of its requisite for the analog design automation. Compared with other two steps the sizing of an analog circuit is the complex one.

Usually, the sizing of analog integrated circuits has synthesis and optimization parts. Based on the user design specifications and circuit topology the synthesis parts create circuit sizes [5]. The design automation of analog circuit synthesis methods divided into knowledge-based and optimization-based approaches. Circuit synthesis using knowledge-based approach creates a design equation for each circuit topology. These design plans are derived from the circuit specifications based on designer experience. The computational speed of knowledge- based approach is fast compared with other synthesize methods. The following designs methods have been implemented using this approach are IDAC [6], BLADES [7], OASYS [8] and ARCHGEN [9]. The design equation of analog circuits and technologies are simplified, it causes the optimal design of circuits in terms of accuracy and robustness.

In optimization-based approach, an optimization process iteratively updates the design variables of the circuit. The optimal sizes of the transistor are obtained from these design variables. An optimization-based design approach can be classified into two types namely, equation-based and simulation-based approach. Equation-based approach creates an analytical equation for a circuit. The optimization process used to evaluate the circuit performance using analytical design equations. Some design method using this approaches are OPASYN [10], STAIC [11], ASTRX/OBLX [12] and GPCAD [13]. The demerits of equation-based approach required long setup time because it takes more time to create design equation than manual design. The accuracy of the circuit performance depends on the analytical equations. This leads to low accuracy and incompleteness of the circuit design.

The simulation-based approach converts the de-sign specification into optimization problem which consists of objective function and constraints which is shown in Fig. 2. Based on the user specifications, input parameters range and constant values the optimization algorithm tries to provide the better solution. This technique iteratively adjusts the design parameter values for getting a global solution.

Fig.2

Simulation-based optimization technique.

Compared with other design techniques the simulation-based method provides the better circuit performances. DELIGHT.SPICE [14], FRIDGE [15], FASY [16], ANACONDA [17] are the simulation-based design method for analog circuit design.

In this work, we introduce a new simulation-based design approach for the CMOS differential amplifier and an operational amplifier circuit design using hybrid GWO algorithm. The GWO optimization algorithm combined with a simplex method to provide the optimal solution for analog circuit.

The rest of the paper is organized as follows. Related work of the simulation-based design approaches is discussed in Section 2. The CMOS circuit design specifications and its performance parameters are presented in Section 3. The simplex technique and GWO are discussed in Section 4. Section 5 describes the simulation result of the proposed work. Finally, Section 6 concludes the paper.

2 A brief review of simulation-based design approach in analog circuit design

The analog circuit sizing based on optimization techniques can be classified into deterministic and meta-heuristic methods. The deterministic method is also called traditional optimization techniques. This technique mostly used for simple optimization problems (using Newton’s methods). The demerits of deterministic methods are given by

This method required a good starting point.

Deterministic methods mostly trap into local optimal solutions.

The objective function always depends on the continuity of input parameters ranges [18].

Due to these issues, the deterministic methods are not suitable for analog circuit sizing. Meta-heuristic methods were proposed to overcome the demerits of deterministic methods.

These methods are mostly suitable for complex optimization problem like analog circuit sizing problems Fig. 3. According to circuit sizing design problem, the meta-heuristic methods are classified as follows

Fig.3

Various types of meta-heuristics algorithms used for analog circuit design.

Evolutionary algorithms

Stochastic algorithms

Swarm intelligence algorithms

In evolutionary algorithm category, the Genetic Algorithm (GA) mostly applied to the analog circuit sizing problem because of its efficiency [19, 20]. GA can find the optimal solution in reasonable time. However, the input parameters setting, the convergence rate of GA is a complex one. The search space ability of GA is reduced by genetic operators (such as Crossover and Mutation). To overcome this issue, the NSGA II was proposed with elitism techniques to increase the convergence rate to the global optimum. Genetic programming [21, 22] and differential evolution [23, 24] are the other types of evolutionary algorithm mainly applied for analog circuit design problems. These algorithm required good starting point to provide better solution. Because the population generation of the algorithm is strongly depend on the initial point. One more drawbacks of the evolutionary algorithm are mostly revisiting the same solution, and there is possible to eliminate the good solutions [25]. For complex analog circuit sizing, these algorithms are more complicated and required large search space for an optimal solution. Since, the evolutionary algorithms mostly suitable for small size analog circuit design.

The simulated annealing [26, 27] and tabu [28] search are the stochastic algorithms used for analog circuit design problem. This algorithm is a direct search method and can avoid global minimum solutions. Generally the accuracy of local search methods strongly depends on starting point. This method does not provide the accurate solutions for analog circuit design. Since, these methods were only applicable to small size circuit problems because of its convergence rate and accuracy towards local solution.

In recent times, most of the researchers use swarm intelligence algorithms for optimization problems because of its smooth implementation [34 –37]. The basic operations of these techniques are inspired by the collective behavior of animals and their organizational capabilities. These algorithms use its intelligence techniques to find global solution as well as to increase convergence rate. In the field of analog circuit sizing, swarm intelligence algorithms provide the better solution than other meta-heuristics algorithm [29 –33]. The merits of swarm intelligence algorithms are low computational cost and relatively high convergence rate. In this paper we proposed a hybrid GWO technique to enhance the accuracy of global solution. Simplex search method is introduced to fine turning global solution of GWO. Especially, for analog circuit sizing this direct search method used to enhance the circuit design performance. Our aim is to minimize power dissipation and to reduce total chip size of the CMOS differential amplifier and CMOS operational amplifier. This paper we propose the hybrid GWO algorithm for the CMOS amplifier circuit sizing. The hybrid version of GWO algorithm improves its performance in terms of exploration and exploitation capabilities.

The major contributions of this paper are as follow as,

The proposed hybrid GWO has some advantages regarding convergence speed and global optimum seeking compared with other swarm intelligence methods reported in the literature.

Applying a hybrid swarm intelligence method to circuit design leads to high accuracy and robustness.

3 CMOS analog circuit design specification

An optimal design process of the CMOS amplifiers consists of the following information, such that the design criteria and the design variables. The design specification of CMOS amplifier is also known as the performance parameters, where these parameters include overall gain, CMRR, power dissipation, etc. In circuit design, the transistors dimensions range, bias current, and load capacitance are considered for design optimization.

The relationship between these specifications are inter related to optimize of the circuit performance. To optimize the length and width of each transistor, the design objective function is developed from the specification of CMOS amplifier. The simulation-based optimization model is developed to optimize the design parameter.

3.1 Design variables of CMOS differential amplifier

A CMOS differential amplifier (Fig. 4) input parameter and supply voltages are given as follows: The positive and negative power supply voltages are denoted by symbol V_D D and V_S S; threshold voltages of NMOS and PMOS transistor is represented by V_tn and V_tp.

Fig.4

Schematic of CMOS differential amplifier.

Where $K_{n'} = μ_{n} \cdot C_{o x}$ and $K_{p'} = μ_{p} \cdot C_{o x}$ are the transconductance parameter of NMOS and PMOS transistors. Where μ_n and μ_p indicates electron and hole mobility of the transistors; C_ox - represents the gate oxide capacitance.

The design steps involved in the differential amplifier circuits are as follows [38]:

Determine the range of I_D5 to satisfy slew rate (SR) $SR = \frac{I_{D 5}}{C_{L}}$ (1)

Determine the values of $\frac{W_{1}}{L_{1}} & \frac{W_{2}}{L_{2}}$ in order to satisfy gain (A_V), where (2)

Determine the values of $\frac{W_{3}}{L_{3}} and \frac{W_{4}}{L_{4}}$ to satisfy the maximum ICMR. $V_{IC (max)} = V_{DD} - V_{SG 3} + V_{tn 1}$ (3) (4)

Where V_SG3 is the source to gate voltage of MOSFET.

Determine the values of $\frac{W_{5}}{L_{5}} and \frac{W_{6}}{L_{6}}$ for the minimum ICMR value. $V_{IC (min)} = V_{SS} - V_{DS 5} + V_{GS 1}$ (5) (6)

Where V_DS- drain to source voltage of MOSFET.

Determine the value of I_D5 to satisfy the power dissipation (P_diss), where $P_{diss} = I_{D 5} (V_{DD} + | V_{SS} |) .$ (7)

3.2 Design variables of CMOS operational amplifier

The basic circuit structure of miller compensated two-stage amplifier shown in Fig. 5.

Fig.5

Schematic of a CMOS operational amplifier.

The analog circuit design consists of the user specifications and design variables. General design procedure and design steps of a CMOS operational amplifier can be summarized below:

Determine the value of SR from I_D5 of the amplifier. $I_{D 5} = SR \times C_{C}$ (8)

Determine the transconductance of the input transistors from C_C and UGB. $g_{m 1} = 2 π \times UGB \times C_{C}$ (9)

Determine the values of $(\frac{W_{1}}{L_{1}}) & (\frac{W_{2}}{L_{2}})$ as (10)

Compute $(\frac{W_{3}}{L_{3}})$ and $(\frac{W_{4}}{L_{4}})$ to find out the value of ICMR_max $\begin{matrix} (\frac{W_{3}}{L_{3}}) = (\frac{W_{4}}{L_{4}}) = \\ \frac{I D_{5}}{K_{p}^{'} [V_{DD} - V_{in (max)} - | V_{tp (max)} | + V_{tn (min)}]^{2}} \end{matrix}$ (11)

Compute $(\frac{W_{5}}{L_{5}})$ and $(\frac{W_{8}}{L_{8}})$ to find out the value of ICMR_min $(\frac{W_{5}}{L_{5}}) = (\frac{W_{8}}{L_{8}}) = \frac{2 I D_{5}}{K_{n}^{'} [V_{DS 5} (sat)]^{2}}$ (12)

Where $\begin{matrix} V_{DS 5} (sat) = V_{in} (min) - V_{SS} - V_{tn} (max) \\ - \sqrt{\frac{I D_{5} L_{1}}{K^{n'} W_{1}}} \end{matrix}$

Compute $(\frac{W_{3}}{L_{3}})$ $(\frac{W_{6}}{L_{6}}) = (\frac{W_{4}}{L_{4}}) (\frac{g_{m 6}}{g_{m 4}})$ (13)

Where g_m6 ≥ 10g_m1

and $g_{m 4} = \sqrt{K_{p}^{'} (W_{4} / L_{4}) I_{D 5}}$

Compute I_D6 $I_{D 6} = \frac{(g_{m 6})^{2}}{2 K_{p} (W_{6} / L_{6})}$ (14)

Find out the ration between I_D6 and I_D5 using $(\frac{W_{7}}{L_{7}})$ $\begin{matrix} (\frac{W_{7}}{L_{7}}) = (\frac{W_{5}}{L_{5}}) (\frac{I_{D 6}}{I_{D 5}}) \end{matrix}$ (15)

Compute power dissipation and gain

$A_{V} = \frac{2 g_{m 2} g_{m 6}}{I_{D 5} . I_{D 6} (λ_{n} + λ_{p})^{2}}$ (16) $P_{diss} = (I_{D 5} + I_{D 6}) (V_{DD} + | V_{SS} |)$ (17)

The cost function of a hybrid GWO is the given by (i.e. The total chip area of an operational amplifier and differential amplifier) $CF = \sum_{i = 1}^{N} (W_{i} \times L_{i})$ (18)

Where N represents the number of transistors, W_i and L_i is the width and length of the transistors.

Vectors structure of CMOS differential amplifier and operational amplifier is considered as follows: $X_{{diff}_{a} mp} = [SR, A_{v}, PD, C_{L}, CMRR]$ (19) $X_{opamp} = [SR, A_{v}, PD, C_{L}, CMRR]$ (20)

The input parameters, technology model, and design specifications of CMOS amplifiers are shown in Table 1. Other circuit design parameters would be optimized by hybrid GWO method (i.e., transistors length and width).

Table 1

Supply voltages, transistor model parameters, and constant values of CMOS amplifier

Amplifier inputs	Values
V_dd (V)	1.8
V_ss (V)	– 1.8
V_tp (V)	– 0.43
V_tn (V)	0.48
K_n (μA/V²)	345
K_p (μA/V²)	55
Technology model	0.18μm

4 Proposed hybrid simplex grey wolf optimization

4.1 Grey wolf optimization (GWO)

GWO algorithm is a population-based meta-heuristics optimization method was invented by Mirajali in 2014 [39]. GWO inspired by the hunting technique and social leadership of grey wolves. These wolves are used to form a mathematical model to perform the optimization. In this model most suitable for the continuous optimization problem. As shown in Fig. 6, grey wolves follow the strict social dominant hierarchy. The wolves have a leadership hierarchy, the most dominating solution is considered as the alpha (α). Alphas are at a top level to take decision for the entire pack. Second and third levels of the hierarchy are named beta (β) and delta (δ) wolves. These two wolves assist the alpha in making a decision and replacing best candidate in case of aging. The wolves have a leadership hierarchy, the most dominating solution is considered as the alpha (α).

Fig.6

Grey wolf social hierarchy.

Alphas are at a top level to take decision for the entire pack. Second and third levels of the hierarchy are named beta (β) and delta (δ) wolves. These two wolves assist the alpha in making a decision and replacing best candidate in case of aging. The lowest level is considered as the omega (Ω), which has the remaining parts of solution and the babysitter in the pack. Optimization in GWO is performed by a group of wolves hunting mechanism. The candidate solution based on hunting techniques is guided by α, β, δ and Ω wolves. The wolf can recognize the prey position and also it has better knowledge to encircle prey. The encircling mechanism of wolves during hunt process is expressed as follows, $D = | C * X_{p} (t) - X (t) |$ (21)

Where C represents the coefficient vectors, t is the current iteration, X_p indicates the prey position vector, and X represents the wolf position vector.

Wolves positions are updated as follows, $X (t + 1) = X_{p} (t) - A * D$ (22)

Where, A-indicates a coefficient vector. The constant A and C value is computed as, $A = 2 a . {rand}_{1} - a$ $C = 2 . {rand}_{2}$

Where, rand₁, rand₂ are the random vectors in [1, 0]. The element a-is linearly decreased from 2 to 0.

Divergence and convergence of wolves were modeled by the coefficient vector A. if |A| >1 the wolves diverge from the prey. Wolves are converged towards the prey when |A| <1. The coefficient vector C indicates barrier in the hunting path. If C > 1, it emphasizes the random prey weights in [0, 2], when C < 1 the wolves deemphasize distance (D) to the prey. These two vectors provide better exploration to the wolves.

The GWO algorithm starts with random sampling method to create the initial population of wolves. A fitness function is computed for the randomly selected wolves. Based on the objective function the first three best wolves are indicated as α, β, and δ respectively. The following formulas are updated α, β, and δ wolves position from the prey. $D_{α} = | C_{1} X_{α} - X (t) |$ (23) $D_{β} = | C_{2} X_{β} - X (t) |$ (24) $D_{δ} = | C_{3} X_{δ} - X (t) |$ (25)

The positions of wolves in the search space is modeled as, $X_{1} = X_{α} - a_{1} * D_{α}$ (26) $X_{2} = X_{β} - a_{2} * D_{β}$ (27) $X_{3} = X_{δ} - a_{3} * D_{δ}$ (28) $X (t + 1) = \frac{X_{1} + X_{2} + X_{3}}{3}$ (29)

Where, X_α, X_β, and X_δ indicates wolves position in the search space. X(t+1) represents the random position of a wolf. The constants C₁, C₂, C₃, a₁, a₂, and a₃ are random vectors, and t represents the number of iteration.

4.2 Simplex method

Nelder-Mead simplex is the local search optimization method, especially applied for unconstrained minimization problems [40]. The simplex method is a local search technique to obtain the optimal local solution using non-derivative operations. The steps of the simplex method are described asfollows:

Find out the cost function values f (X_g) , f (X_b) and f (X_s), where X_g represents the best point, X_b represents the second best point and X_s represents the worst point.

Calculated the middle point of X_g and X_b $X_{c} = \frac{X_{g} + X_{b}}{2}$ (30)

The reflection point X_r is calculated as, $X_{r} = X_{c} + α (X_{c} - X_{s})$ (31)

Where, α indicates reflection factor (α = 1).

If f (X_r) < f (X_g), then the reflection process were moving in right direction. The expansion point X_e is calculated as, $X_{e} = X_{c} + γ (X_{r} - X_{c})$ (32)

Where, γ indicates the contraction factor (γ = 0.5). If f (X_e) < f (X_g), then replace X_s into X_e, else replace X_s into X_r.

if f (X_r) > f (X_s), then perform the compression operation as follows $X_{t} = X_{c} + β (X_{s} - X_{c})$ (33)

Where, β indicates the compression factor (β = 0.5). If f (X_t) < f (X_s), then replace X_s into X_t, else replace X_s into X_r.

If f (X_g) < f (X_r) < f (X_s), then perform the shrink operation for the compression point of X_W. The compression point is expressed as:

$X_{w} = X_{c} - β (X_{s} - X_{c})$ (34)

If f (X_w) < f (X_s), then replace X_s into X_w, else replace X_s into X_r.

4.3 Proposed hybrid grey wolf optimization method for circuit sizing

The ultimate aim of GWO is to find the optimal value over the number of iterations, and arrange the population toward the better solution. In case of GWO algorithm, there is possibility to traps in local solution, this will cause the stagnation problem. To avoid this problem we are introduce simplex method to find the final minimum value. Hence, the simplex method find the local optimal value in the neighborhood search space. During the GWO course of iteration, we use simplex method to strengthen the local optimal solution. Simplex methods provide the better individual solution more easily and also efficiently explore the design search space.

The details explanation of hybrid GWO is found in [41]. A simplex method used to improve the local search exploitation of GWO.

The design steps of Hybrid GWO are given as follows:

Step 1. Initialize populations and define the input parameters of grey wolf optimization algorithm.

Step 2. Calculate the fitness of each and every search agent. Using fitness value best three search agents are selected for evaluation.

Step 3. The best agent is considered as the elite individual for opposition learning technique and updates the boundaries values.

Step 4. Calculate the fitness values of individuals and update the current search agent

Step 5. Find the best solution value using simplex method

Step 6. Continue iterations from step 3 until the end conditions are satisfied.

The pseudo code of hybrid GWO with simplex approach is provided below

Pseudo code of Hybrid GWO.

Define the cost function and initialize the design parameters and population X_i

Determine the initial fitness value for each search agent

Define X_α, X_β and X_γ are the first, second and third agent respectively

While (t < MaxGen)

for each search agent

Update the position of each agent

end for

Update the value of design parameter

Determine the fitness values of each agent

Update first, second and third best agent

determine the current best value using simplex method

t = t+1

end while

Return to first best agent (X_α)

5 Simulation result and discussion

The proposed hybrid GWO algorithm based simulation model has been implemented in Matlab for the design optimization of CMOS differential amplifier and an operational amplifier. The simulation result is compared with the existing simulation-based design approaches. The input parameters and constant values of amplifiers are given in Table 1.

The main objective of this simulation-based approach is to minimize the chip size and to reduce the power dissipation of amplifier circuits. The design constraints of an algorithm are to satisfy the design criteria of the circuits. The circuit sizing problem has been constructed as the minimization of the cost function for each amplifier circuit. For the design of the CMOS differential amplifier and operational amplifier circuits, hybrid GWO is applied to find out the transistor dimensions (length and width of the transistor) and bias current values.

5.1 Simulation result of a CMOS differential amplifier

This section described the result of CMOS differential amplifier circuit sizing using GWO algorithm with other simulation-based approaches. The optimal design parameter values of the differential amplifier shown in Table 2. Compared with other two methods the proposed method provides the better result in terms of transistor sizes as well as bias current values. The design specifications obtained from the hybrid GWO is shown in Table 3. The power dissipation and total area of the chip are minimized using the proposed method. The hybrid GWO method also improves the DC gain of differential amplifier compared with other simulation-based techniques. Therefore, the proposed hybrid GWO method provides the optimal circuit sizes for the design of CMOS differential amplifier. Figure 7 shows the comparison of the operational amplifier power dissipation with other simulation-based methods such as Darwin optimization and PSO techniques.

Table 2
CMOS differential amplifier design parameters

Design parameters Proposed method

W₁/L₁ (μ m/μ m) 15.31/1.2

W₂/L₂ (μ m/μ m) 15.31/1.2

W₃/L₃ (μ m/μ m) 35.7/1.2

W₄/L₄ (μ m/μ m) 35.7/1.2

W₅/L₅ (μ m/μ m) 49.95/1.2

W₆/L₆ (μ m/μ m) 49.95/1.2

I_bias (μ m/μA) 53

C_L (pF) 5

Design parameters	Proposed method
W₁/L₁ (μ m/μ m)	15.31/1.2
W₂/L₂ (μ m/μ m)	15.31/1.2
W₃/L₃ (μ m/μ m)	35.7/1.2
W₄/L₄ (μ m/μ m)	35.7/1.2
W₅/L₅ (μ m/μ m)	49.95/1.2
W₆/L₆ (μ m/μ m)	49.95/1.2
I_bias (μ m/μA)	53
C_L (pF)	5

Table 3

CMOS differential amplifier circuit specifications and results

Design specifications	Constraints	Darwin [19]	PSO [31]	Proposed method
Output capacitance (pF)	≥5	2	5	5
Slew Rate (V/μs)	≥10	3.2	22.4	12.4
Power dissipation (μW)	≤2000	31	1260	265
Phase margin (°)	>45	72	83.8	82
Gain (d_B)	>40	60	42	41.06
CMRR (d_B)	>40	–	84.2	82.9
Area (μm²)	<300	6500	296	242

Fig.7

Power dissipation of differential amplifier circuit.

5.2 Simulation result of CMOS operational amplifier

This section described the result of CMOS operational amplifier circuit sizing using GWO with other simulation-based methods. The optimal design parameter values of an operational amplifier shown in Table 4. Compared with other two methods the proposed method provides the better result in terms of transistor sizes as well as bias current values. The design specifications obtained from the hybrid GWO is shown in Table 5. The convex optimization and PSO methods dissipate more power than proposed optimization methods. The other parameters of the operational amplifier are also improved using hybrid GWO simulation-based approach. In this work, we are concentrating on the operational amplifier gain, slew rate and unity gain bandwidth (UGB). Because these parameters are important for design a CPS system for specific application. Signal range can be controlled by the UGB of the operational amplifier.

Table 4
Design parameters of CMOS operational amplifier

Design parameters Proposed method

W₁/L₁ (μ m/μm) 6.2/1.4

W₂/L₂ (μ m/μm) 6.2/1.4

W₃/L₃ (μ m/μm) 9.4/1.4

W₄/L₄ (μ m/μm) 9.4/1.4

W₅/L₅ (μ m/μm) 10.5/1.4

W₆/L₆ (μ m/μm) 22.6/1.4

W₇/L₇ (μ m/μm) 14.5/1.4

W₈/L₈ (μ m/μm) 10.5/1.4

C_L (pF) 12

C_c (pF) 3.2

I_bias (μA) 32

Design parameters	Proposed method
W₁/L₁ (μ m/μm)	6.2/1.4
W₂/L₂ (μ m/μm)	6.2/1.4
W₃/L₃ (μ m/μm)	9.4/1.4
W₄/L₄ (μ m/μm)	9.4/1.4
W₅/L₅ (μ m/μm)	10.5/1.4
W₆/L₆ (μ m/μm)	22.6/1.4
W₇/L₇ (μ m/μm)	14.5/1.4
W₈/L₈ (μ m/μm)	10.5/1.4
C_L (pF)	12
C_c (pF)	3.2
I_bias (μA)	32

Table 5

CMOS operational amplifier circuit specifications and results

Design specifications	Constraints	Convex optimization [21]	PSO [31]	Proposed method
Output capacitance (pF)	≥10	3	10	12
Slew Rate (V/μs)	≥10	88	11.13	10.2
Power dissipation (μW)	≤2500	5000	2370	1600
Unity gain bandwidth (MHz)	≥5	86	5.32	8.63
Phase margin (°)	>60	60	66.55	52
Gain (dB)	>60	89.2	63.8	75.3
CMRR (dB)	>80	92.5	83.74	81
Area (μm2)	<300	8200	265	125

The power dissipation and the total area are minimized by the proposed simulation-based method. Therefore, the proposed hybrid GWO method provides the optimal circuit sizes for the design of CMOS operational amplifier. Figure 8 shows the comparison of the operational amplifier power dissipation with other simulation-based methods such as convex optimization and PSO techniques.

Fig.8

Power dissipation of operational amplifier circuit.

6 Conclusion

In this paper, a hybrid GWO algorithm using simplex search based analog integrated circuit design for cyber-physical system (CPS) is proposed. The learning approach has been combined with swarm intelligence technique to improve the convergence rate of an optimization method. The CMOS amplifier circuits are optimized by the design variables like transistor sizes, bias current, and load capacitance. Hence, the hybrid GWO is capable of find out transistor dimensions and bias current values for the CMOS differential and operational amplifier circuits. The proposed simulation-based design approach successfully meets the circuit design specifications of the CMOS amplifier circuits. Therefore, we concluded that the optimal design of CMOS amplifiers using hybrid GWO is the best simulation-based approach compared with other reported methods.

Footnotes

Acknowledgments

The authors wish to thank TCS and SASTRA Deemed University for providing technical facilities to carry out this work.

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Optimization and control of CMOS analog integrated circuits for cyber-physical systems using hybrid grey wolf optimization algorithm

Abstract

Keywords

1 Introduction

3.1 Design variables of CMOS differential amplifier

4.1 Grey wolf optimization (GWO)

5 Simulation result and discussion

5.1 Simulation result of a CMOS differential amplifier

Table 2 CMOS differential amplifier design parameters Design parameters Proposed method W1/L1 (μ m/μ m) 15.31/1.2 W2/L2 (μ m/μ m) 15.31/1.2 W3/L3 (μ m/μ m) 35.7/1.2 W4/L4 (μ m/μ m) 35.7/1.2 W5/L5 (μ m/μ m) 49.95/1.2 W6/L6 (μ m/μ m) 49.95/1.2 Ibias (μ m/μA) 53 CL (pF) 5

Footnotes

Acknowledgments

References