Fractional order controller design for SEPIC converter using metaheuristic algorithm

Abstract

Fractional order proportional, Integral and a derivative controller is a special kind of controller which is used to regulate the output voltage of a class of sepic converter to the desired level. Tuning of fractional Proportional, Integral and Derivative controller (FOPID) is achieved by different metaheuristic algorithm and the optimization performance target is chosen as minimizing the integral square error (ISE). This paper presents a performance analysis of Single Ended Primary Inductance Converter (SEPIC) by time response specifications such as rise time, settling time and steady-state error and further, the results are compared with the controllers designed by Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Queen Bee based Genetic Algorithm (QBGA). The design and implementation of fractional order controller for a closed loop control of converter is done by utilizing a MATLAB/SIMULINK environment. Results show that QBGA algorithm exhibit better performance as compared to other optimization technique for voltage mode controller in terms of disturbance rejection.

Keywords

SEPIC converter fractional PID controller GA PSO QBGA

1 Introduction

DC-DC converters have been widely used in industrial applications such as communication equipment, computer systems, electric vehicle charging and DC motor drives due to its buck-boost abilities. There are different types of DC converters such as boost, buck, and buck-boost converters are required for different applications. Buck-boost converter has an inverted output, high voltage stress and pulsating input current. These drawbacks can be overcome by SEPIC converter. The SEPIC converter is a type of DC-DC converter allowing the voltage at its output to be less than, greater than, or equal to that of its input with the ability to provide noninverting polarity with respect to the input voltage. This converter acts as a buck-boost converter due to its voltage gain flexibility. By varying the duty cycle of the converter from 0 to 1 the output voltage can be varied.

Generally, the sepic converters are inherently nonlinear characteristics due to the operation of switching devices and load variations. The response of the sepic converter is easily influenced by external disturbances. The SEPIC converter shown in Fig. 1 has two inductors, two capacitors and a power switch thus it is a fourth order nonlinear system and also exhibits nonminimum phase system. Due to these nonlinearities, the stability analysis, designing and evaluating the controllers are difficult. The converter is stable when operating under nominal operating conditions for small perturbation in linearized and small signal model [1]. Many controlling techniques like sliding mode, back stepping can be used for nonminimal phase systems while for minimal phase systems modal reference adaptive control technique is required [2]. The transfer function of the new inverter topology for the positive and negative cycle is derived and the control to output transfer function is analyzed using root locus [3]. The root locus method is studied for variation in components value to determine the shift of the poles and zeros of the system. Model order reduction method is used for a controller design of Sepic converter [4]. The Pade approximation technique is used to reduce the fourth order transfer function to second order function.

Fig.1

SEPIC converter topology.

The behavior of the sepic converter with continuous conduction mode (CCM) and all parasitic elements included can be analyzed and various studies regarding some parameter perturbations of the converter can be performed. This paper presents with the design of fractional controller and control implementation of a SEPIC converter and also changes the unregulated DC output voltage to regulated DC output voltage. Fractional order PID controller is a special kind of PID controller, whose integral and derivative order is fractional rather than an integer. The design of the fractional controller is to find the appropriate controller parameter in such a way to minimize the cost function of ISE. These can be achieved by using optimization technique like Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Queen Bee based GA (QBGA) algorithm. The design and implementation of the fractional controller is done by using Matlab/Simulink.

2 SEPIC converter topology

The simplified equivalent circuit diagram for SEPIC converter is depicted in Fig. 1. The inductor equivalent resistor and capacitor equivalent resister are included in this analysis. SEPIC converter has two modes of operation, either continuous conduction mode (CCM) or discontinuous conduction mode (DCM). Here the SEPIC converter operated in Continuous conduction mode. In CCM mode the inductor current never falls to zero during one switching period. The amount of energy exchanged between inductor and capacitors is controlled by the control transistor. During the steady-state operation, the voltage appears across the capacitor C₁ is equal to the input voltage.

3 State space modeling of SEPIC converter

There are so many methods available for modeling of DC-DC power converters like state space averaging (SSA) method. State space representation is a mathematical model of the system that describes the system by a set of linear differential equations. State space analysis of SEPIC converter for continuous conduction mode can be done in two modes of operation.

There are two circuit states when the switch is operated. Consider the state space model of the converter when a switch is closed for the duration of period (0 < t < dT), $\begin{matrix} x (t) = A_{1} x (t) + B_{1} u (t) \\ y (t) = C_{1} x (t) + D_{1} u (t) \end{matrix}$ (1)

The state space averaged matrices model of the SEPIC during ON state,

$\begin{matrix} [\begin{matrix} i_{L 1} \\ i_{L 2} \\ V_{C 1} \\ V_{C 2} \end{matrix}] & = & [\begin{matrix} - \frac{r_{L 1}}{L_{1}} & 0 & 0 & 0 \\ 0 & - \frac{(r_{C_{1}} + r_{L_{2}})}{L_{2}} & \frac{1}{L_{2}} & 0 \\ 0 & - \frac{1}{C_{1}} & 0 & 0 \\ 0 & 0 & 0 & - \frac{1}{C_{2} (R + r_{C_{2}})} \end{matrix}] \\ \times [\begin{matrix} i_{L 1} \\ i_{L 2} \\ V_{C 1} \\ V_{C 2} \end{matrix}] + [\begin{matrix} \frac{1}{L_{1}} \\ 0 \\ 0 \\ 0 \end{matrix}] V_{in} \end{matrix}$ (2)

The output voltage during switch ON is given by $V_{0} = \frac{R_{A} V_{C 2}}{r_{C 2}}$ (3) and when a switch is opened for duration of a period (dT < t < (1-D) T) $\begin{matrix} x (t) = A_{2} x (t) + B_{2} u (t) \\ y (t) = C_{2} x (t) + D_{2} u (t) \end{matrix}$ (4)

The state space averaged matrices model of the SEPIC during OFF state is given by $[\begin{matrix} i_{L 1} \\ i_{L 2} \\ V_{C 1} \\ V_{C 2} \end{matrix}] = [\begin{matrix} \frac{C_{2} R_{A} - C_{1} (r_{L_{1}} + r_{C_{1}})}{L_{1} C_{1}} & \frac{L_{2} r_{L_{2}} + L_{1} r_{L_{2}} - L_{1} R_{A}}{{L_{1}}^{2}} & - \frac{1}{L_{1}} & 0 \\ \frac{C_{2} R_{A}}{C_{1} L_{2}} & \frac{R_{A} - r_{L_{2}}}{L_{2}} & 0 & \frac{R_{A}}{L_{2} r_{C_{2}}} \\ \frac{1}{C_{1}} & 0 & 0 & 0 \\ \frac{R_{A}}{C_{1} r_{C_{2}}} & \frac{R_{A}}{C_{2} r_{C_{2}}} & 0 & - \frac{1}{C_{2} (R_{L} + r_{C_{2}})} \end{matrix}] [\begin{matrix} i_{L 1} \\ i_{L 2} \\ V_{C 1} \\ V_{C 2} \end{matrix}] + [\begin{matrix} \frac{1}{L_{1}} \\ 0 \\ 0 \\ 0 \end{matrix}] V_{in}$ (5)

The output voltage during switch OFF is given by $V_{0} = R_{A} i_{L 1} + R_{A} i_{L 2} + \frac{R_{A} V_{C 2}}{r_{C 2}}$ (6) where $R_{A} = \frac{R_{L}}{R_{L} + R_{C 2}}$ (7)

The inductor current i_L1, i_L2 and capacitor voltages V_C1, V_C2 are taken as state variables.

4 Fractional order PI^λD^μ controller design

In recent years the application of fractional calculus is increased in the field of science and engineering [5]. Fractional order controllers have been used in industrial applications such as power electronics [6], Robotic manipulators [7] and system identification [8]. A Strength Pareto Evolutionary Algorithm (SPEA) method of designing optimal integer and fractional order PID controllers for a boost converter to gain a set of favorable characteristic at various operating points is discussed in [9]. The quantitative robustness evolution of PID controllers of DC motor is performed employing a 2³ factorial experimental design for a fractional order PID controller [10].

Fractional order control systems are described by fractional order differential equations. There are several definitions of fractional derivative [11]. Grunewald- Letnikov definition is best suitable for realization of the control systems. The general continuous Integro – differential operator of order α ∈ R is defined as

$a D_{t}^{r} = {\begin{matrix} \frac{d^{α}}{d t^{α}}, R (α) > 0 \\ 1, R (α) = 0 \\ \int_{a}^{t} {(dt)}^{- α}, R (α) < 0 \end{matrix}$ (8) where α represents the real order of differ-integrator operator t is the parameter for which the differential-integral is taken and a is the lower limit. The orders of integral and derivative are not necessarily an integer, but any real numbers.

Based on the concept of differentiation Grunewald Letnikov definition is given by ${a D}_{t}^{α} f (t) = \lim_{h \to \infty} \frac{1}{\overset{α}{h}} \sum_{j = 0}^{[\frac{t - a}{h}]} {(- 1)}^{j} (\begin{matrix} a \\ j \end{matrix}) f (t - jh)$ (9) where $w_{j}^{α} = {(- 1)}^{j} (\begin{matrix} a \\ j \end{matrix})$ represents the coefficients of a polynomial (1 - z) ^α.

Riemann – Liouville definition: ${a D}_{t}^{- α} f (t) = \frac{1}{Γ (α)} \int_{a}^{t} {(t - τ)}^{α - 1} f (τ) d τ$ (10)

Where 0 < α < 1 and a is the initial time instance, assumed to be zero, i.e.., α= 0.

The Laplace transform of the above equation is given by $\int_{0}^{\infty} e^{-st} {0D}_{t}^{-α} f (t) {dt=s}^{-α} F (s) - \sum_{p=0}^{m-1} s^{k} {0D}_{t}^{α-p-1} f (t)$ (11)

Normally integer order PID controllers are widely used in most industries due to its simplicity and easiest tuning. The performance of the PID controller can be improved by making use of fractional integrals and derivatives. The power electronic buck converter was successfully controlled by applying fractional order controller. In order to apply a fractional sliding mode control scheme to the control of device, the proposed method uses the fractional calculus in the determination of the switching surface [12]. The use of sliding mode approaches based on fractional order control is discussed [13].

A fractional controller is the expansion of conventional PID controller based on fractional calculus which is generalized by Podlubny [14] and expands it from point to plan shown in Fig. 2. Tuning methods of PI^λD^μ controllers are new research subject [15 –17]. This type of controller has five parameters to be tuned. This flexibility can help the design of the system more robust and also enhance the optimal control performance.

Fig.2

PID controller with fractional order.

The continuous transfer function of a fractional controller with five adjustable parameters is given by the following function [18]. $G_{C} (S) = K_{p} + \frac{K_{i}}{S^{λ}} + K_{d} S^{μ} where (λ, μ > 0)$ (12) $G_{C} (S) = K_{c} (1 + \frac{1}{τ_{i} S^{λ}} + τ_{d} S^{μ})$ (13)

The differential equation of the fractional order controller PI^λD^μ is defined in Equation (14). $u (t) = K_{p} e (t) + K_{i} D^{- λ} e (t) + K_{d} D^{μ} e (t)$ (14) where λ, μ are positive real numbers. If λ= 1 and μ= 1 the controller becomes integer PID and if lambda, μ is fractions than it becomes a fractional controller.

To regulate the output voltage of the SEPIC converter a feedback controller is designed. Being of higher order converter, the behavior of SEPIC is nonlinear and depends on load variations and operating conditions. The working condition of the SEPIC converter with good dynamics at any operating point could be ensured by optimum controllers. In this paper, a fractional order controller is used to regulate the DC output voltage.

The closed loop voltage control of SEPIC converter with fractional order PID controller is shown in Fig. 3. The output voltage V₀ is compared with the reference voltage V_ref and the error voltage is then passed through the compensator. The generated control signal is compared with the sawtooth waveform and then it is used to drive the switch. The output of a comparator is gating pulse with its duty cycle varying in accordance with fractional PID controller output voltage. The regulated output voltage is obtained by adjusting the duty cycle of the switch until the output voltage is equal to a reference voltage.

Fig.3

SEPIC converter with PWM feedback controller.

5 Problem formulation

The design of a controller is a challenge to meet a set of specifications in the time domain which define the overall performance of the converter. The specifications mentioned here as a dynamic response of the system to step input. In order to design and measure the performance of the controller, the Integral Square Error performance criteria are considered as a fitness function. The design of the fractional controller is formulated as an optimization problem which is given as $\begin{matrix} Minimize F (φ) = \sum_{t = 0}^{T} {(e (t))}^{2} \\ Subject to φ_{min} < φ < φ_{max} \end{matrix}$ (15) where φ_min and φ_max are minimum and maximum of variables φ ={ k_p, k_i, k_d, λ and μ }.

Minimization of ISE by adjusting controller parameters is a compromise between the reductions of transient response characteristics.

6 Computational algorithm for tuning the parameters of the FOPID controller

Optimization is finding the parameter combination which gives the best performance among all feasible combinations of parameters. According to control objective for a fractional order controller, five variables k_p, k_i, k_d, λ and μ need to be approximated. Since tuning of fractional controllers needs large search space, nature inspired optimization algorithms are generally employed. These controller parameters are tuned to achieve the cost function by using optimization algorithms such as Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Queen Bee based GA (QBGA) algorithm. A controller tuning based on optimization strategies are discussed in [19].

Figure 4 shows the proposed methodology to design a fractional controller for SEPIC converter based on the above three optimization algorithm. The objective function for controller tuning in all heuristic algorithms is same as Equation (15), and the termination criteria is referred to as the number of iterations. Due to the flexibility of heuristic algorithm the application of this algorithm can easily be adapted to design of controllers.

Fig.4

SEPIC converters with FOPID controller.

6.1 QBGA tuning of controller

The optimization problems with the objective function are solved by using a heuristic algorithm due to its simplicity, speed of response and better optimization ability. Queen Bee based GA is the one among the optimization technique which is used to obtain the controller parameters by evaluating the objective function Equation (15). The optimization design of feedback controller for dc-dc boost converter by QBGA is discussed and also verified, that this algorithm converges to the best design for a limited number of iterations [20]. The queen bee algorithm is based on the interactions of bees in a hive. Queen bee plays a vital role in reproduction process and the fittest individual in a generation cross breeds with the other bees selected as parents by a selection algorithm. Queen Bee algorithm could improve the performances of the genetic algorithms by reinforcing both exploitation and exploration of genetic algorithms. That is offspring mainly depending on the crossover operation and the fittest individual. As a result, it also increases the probability of premature convergence and also quickly approaches the global optimum [21].

The search process continues until stopping criteria is satisfied. Here the number of iteration is referred to as stopping criteria.

The sequential steps of the queen bee GA are summarized below

Generation of Bees (One bee refers to as one complete solution) in a feasible solution space.

Identification of queen bee: The selected queen bee is the best binary structure for minimizing the cost function.

Reproduction: Drones mate with queen bee produce two offsprings. Among the two the fittest alone survives and other is discarded and is equivalent to the virgin queen bee.

Every virgin queen bee competes with current queen whichever survives become the new nest queen.

Terminate the program and select the new queen bee as an optimal solution.

This iteration is repeated several times by regenerating drones until the best optimal solution is found.

The operational flowchart for a genetic algorithm with queen bee evolutionary algorithm is shown in Fig. 5.

Fig.5

Optimization flow chart for QBGA Algorithm.

6.2 Parameter selection

The optimization of the controller parameters is obtained by evaluating the objective function by using a Genetic Algorithm, Particle Swarm Optimization and Queen Bee based GA. The selection of parameter for the different algorithm plays a vital role for various problems.

The main parameters of genetic algorithm and queen bee based genetic algorithm namely crossover rate and mutation rate are investigated. Mutation rate is randomly selected in the range between 0.01 and 0.1. The good sets of chromosomes are considered as optimal controller parameter and are kept whereas worst chromosomes are left out. Then the ISE value of the good chromosomes is checked to find out if these are the best optimal chromosomes. To get more optimal results, mutation operation is performed. The process is repeated until the objective function value ISE is satisfied.

Kennedy and Eberhart originated the original framework of PSO in 1995. Particle Swarm Optimization belongs to the field of swarm intelligence which is inspired by the social foraging behavior of some animals such as flocking behavior of birds and the schooling of fish. The comprised collection of particles in a PSO is moved around the search space influenced by their own best past location and the best past location of the whole swarm. The particle’s velocity in each iteration is updated using $V_{i}^{t + 1} = W^{t} \cdot V_{i}^{t} + C_{1} R_{1} (P_{i}^{t} - S_{i}^{t}) + C_{2} R_{2} (G_{i}^{t} - S_{i}^{t})$ (16)

A particle’s position is updated by using Equation (17) $S_{i}^{t + 1} = S_{i}^{t} + V_{i}^{t + 1}$ (17)

The numerical coefficients consisting of momentum factor, societal factor, inertia weight and an individual factor of PSO influence the optimization performance.

All the above algorithms stop, when the specified maximum number of iterations is reached. The parameters of these three different algorithms used here are specified in Tables 1 and 2 respectively is implemented for the cost function ISE.

Table 1

Selected values of parameters for GA and QBGA algorithms

	GA	QBGA
Number of dimensions	5	5
Population size	20	20
Chromosome structure	Binary coding	Binary coding
Selection scheme	Roulette wheel	Best bee as queen
Mutation rate/probability	0.1	0.1
Crossover rate/probability	0.6	0.1

Table 2

Selected values of parameters for PSO algorithm

Particle swarm optimization (PSO)
Population size	10
Number of dimensions	5
Number of particles	20
C₁ = C₂	1.5

7 Simulation results and discussion

The simulation results presented in this section are developed using MATLAB / SIMULINK. The design specifications of SEPIC converter considered in this paper are given in Table 3. The tuned parameters of the fractional controller are obtained by the optimization algorithm.

Table 3
SEPIC design parameters

Circuit parameters Values

Input voltage V_in 10V

Output voltage V_o 10V

Switching frequency 50kHz

Load R 10Ω

L₁, L₂ 150μH

r_L1, r_L2 0.07Ω

C₁, C₂ 100μF

r_c1, r_c2 0.008Ω

Circuit parameters	Values
Input voltage V_in	10V
Output voltage V_o	10V
Switching frequency	50kHz
Load R	10Ω
L₁, L₂	150μH
r_L1, r_L2	0.07Ω
C₁, C₂	100μF
r_c1, r_c2	0.008Ω

The unit step responses of the SEPIC converter with GA, PSO, and QBGA controllers are shown in Fig. 6(a-c).

Fig.6

Step Response of Sepic convertor for different algorithms. (a) GA algorithm; (b) PSO algorithm; (c) QBGA algorithm.

In order to obtain the global best solution with high probability, the given nature-inspired optimization problem should be solved more times. The dynamic performance analysis of SEPIC converter in terms of transient response characteristics such as rise time, settling time and steady-state error for each controller gain parameters obtained from different algorithms are specified in Table 4. All the simulation results of SEPIC converter for step responses are shown by the help of Matlab/Simulink environment for the fourth order SEPIC converter which is controlled by a fractional controller.

Table 4

Controller gain and time response specifications

Controller	K_p	K_i	Lamda	K_d	μ	Rise time	Settling time	Steady state error	Minimum of J_ISE
GA-FOPI	0.03144	0.001011	0.01017	0.00011	0.01048	2.032e-04	0.0042	0.0420	0.02953
PSO-FOPI	0.03000	0.008018	0.06781	0.00500	0.01691	2.032e-04	0.0042	0.0420	0.02953
QBGA-FOPI	0.06735	0.001739	0.01447	0.00045	0.02245	1.808e-04	0.0034	0.0330	0.01913

From the Table 4, it can be concluded that the transient behavior of the SEPIC converter for GA and PSO is almost same. The performance characteristic of the SEPIC converter can be improved and also the fitness function is minimized by using Queen Bee based Genetic Algorithm.

The stability of the system is verified by a change in load resistance and also change in output reference value.

The tuned controller parameter which is obtained by optimization algorithm is considered for a change in load resistance and the reference voltage. The variation of the output voltage when a step changes in load resistance from 10 Ω to 15 Ω at time t = 0.0075 seconds is illustrated in Fig. 7. It is observed that the output voltage remains constant. The reference voltage is changed from 10V to 12V. The converter output voltage settles to the set value after an overshoot as shown in Fig. 8. The all designed fractional order PID controller for SEPIC a converter tracks the reference output voltage when the load side disturbance and change in reference voltage.

Fig.7

Output voltage when a step Change in Load Resistance from 10 Ω to 15 Ω at time t = 0.0075 s.

Fig.8

Change in Reference voltage from 10 to 12V and back to 10V.

8 Conclusion

In this paper, an optimal design method of the fractional controller has been presented and further, the dynamic behavior of the SEPIC converter is studied. The GA, PSO and QBGA optimization algorithm has been utilized to find the optimal parameters of FOPID controller which minimizing the Integral Square Error (ISE). The stability of the SEPIC converter is verified by a change in load resistance and a step change in reference voltage. The results obtained by these controllers are compared in terms of various time domain transient response characteristics of the algorithm. From these observed results, it is found that SEPIC converter with QBGA controller exhibits better performance, disturbance rejection and robust response as compared to other controller algorithms. It is also observed that the output voltage is better regulated when the fractional order PID controller is applied.

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Fractional order controller design for SEPIC converter using metaheuristic algorithm

Abstract

Keywords

1 Introduction

3 State space modeling of SEPIC converter

Table 3 SEPIC design parameters Circuit parameters Values Input voltage V i n 10V Output voltage V o 10V Switching frequency 50kHz Load R 10Ω L1, L2 150μH rL1, rL2 0.07Ω C1, C2 100μF rc1, rc2 0.008Ω

References

Table 3
SEPIC design parameters

Circuit parameters Values

Input voltage V_in 10V

Output voltage V_o 10V

Switching frequency 50kHz

Load R 10Ω

L₁, L₂ 150μH

r_L1, r_L2 0.07Ω

C₁, C₂ 100μF

r_c1, r_c2 0.008Ω