Optimal concurrency on FPGA for lightweight medical image encryption

Abstract

Digitized forms of images do widely used for medical diagnostics. To maintain the privacy of an individual in e-health care applications, securing the medical image becomes essential. Hence exclusive encryption algorithms have been developed to protect the confidentiality of medical images. As an alternative to software implementations, the realization of image encryption architectures on hardware platforms such as FPGA offers significant benefit with its reconfigurable feature. This paper presents a lightweight image encryption scheme for medical image security feasible to realize as concurrent architectural blocks on reconfigurable hardware like FPGA to achieve higher throughput. In the proposed encryption scheme, Lorentz attractor’s chaotic keys perform the diffusion process. Simultaneously, the pseudo-random memory addresses obtained from a Linear Feedback Shift Register (LFSR) circuit accomplishes the confusion process. The proposed algorithm implemented on Intel Cyclone IV FPGA (EP4CE115F29C7) analyzed the optimal number of concurrent blocks to achieve a tradeoff among throughput and resource utilization. Security analyses such as information entropy, histogram, correlation, and PSNR confirms the algorithm’s encryption quality. The strength of diffusion keys was ensured by randomness verification through the standard test suite from the National Institute of Standards and Technology (NIST). The proposed scheme has a larger keyspace of 2³⁸⁴ that guarantees good confusion through near-zero correlation, and successful diffusion with a PSNR of <5 dB towards the statistical attacks. Based on the hardware analysis, the optimal number of concurrent architectural blocks (2 ^N) on the chosen FPGA to achieve higher throughput (639.37 Mbps), low power dissipation (138.85 mW), minimal resource utilization (1268 Logic Elements) and better encryption quality for the proposed algorithm is recommended as 4 (with N = 2).

Keywords

Concurrency lightweight lorentz attractor FPGA and encryption

1 Introduction

Employing e-health security solutions has become an emerging trend globally due to the fascinating evaluation of telemedicine applications [1]. Digital Imaging and Communications in Medicine (DICOM) is one among the medical image format that has been recommended by the National Electrical Manufacturers Association (NEMA) [2 –4]. When shared across a wide range of network, these medical images become vulnerable to several attacks such as side-channel, man in the middle, occulation, cropping, etc. [5, 6]. Usually, medical images are considered in larger sizes having grater pixel depth with more redundancy and strong correlation between its adjacent pixels. Hence, the conventional encryption algorithms like AES, DES, and IDEA are regarded as less suitable to secure medical images[5 , 7–10]. Nowadays, image-specific cryptographic solutions specifically designed to preserve medical images have captivated researchers’ attention [8].

The researchers proposed several techniques addressing medical images’ security by implementing encryption algorithms on the software platform, such as Matlab. Dhivya et al. [11] proposed a scheme for encrypting colour DICOM images. In [11] the use of chaotic keys generated from coupled logistic tent and sine map results in a larger keyspace of 10²⁶⁸ with nearly zero correlation among the adjacent pixels of the encrypted image achieved via DNA based diffusion process. The Edge Map-based Medical Image Encryption (EMMIE) algorithm proposed by Weijia cao et al. [12] suggests combining biplane decomposition, random sequence generation and permutation processes at an enhanced keyspace in the order of 10³²⁷ to mitigate brute force attack. The algorithm by Jeyamala Chandrasekaran et al. [13] proposed the integration of number theory and chaotic Henon map to generate a unique random key to encrypt each pixel of the DICOM image. Though this approach has offered a higher level of encryption which has been resulted in accomplishing low PSNR value of 6.7370 dB, the reduced entropy of 7.1023 (against the maximum value of 8) measured on the encrypted image shows the lack of randomness in the encrypted pixel values. The use of permutation-substitution-diffusion sequence with logistic-Chebyshev, DNA encoding and sine-Chebyshev was developed by AkramBelazi et al. [14] for the encryption of medical images. This approach has offered almost a zero correlation (0.0008) with a global entropy value of 7.9993 and a larger keyspace (2⁷¹⁶).

Software implementation of security architectures achieves better performance with limitations in terms of time complexity, flexibility and vulnerability to attacks [15]. Reconfigurable / resource-constrained hardware platforms like FPGA and microcontrollers are preferred predominantly to build prototypes with faster time to market for image security through lightweight watermarking and encryption schemes [16 –18]. Further, embedded hardware platforms such as FPGAs also address the issues concerned with software implementations.

In [7], The chaotic RGB image encryption algorithm implemented in cyclone II FPGA in [7], encrypts a 256×256 RGB image in 28.22 ms when operated at 50 MHz and dissipates 210 mW of power. Sundararaman et al. [6] performed similar RGB image encryption with Lorentz and l? chaotic attractor. Implementing on the same cyclone II FPGA hardware could minimize the encryption time by approximately 50% (14.73 ms) against [7] while offering better correlation and entropy with improved keyspace. A Penta layer security scheme by Dhivya et al. [19] used the chaotic clocks generated by PLL of the cyclone II FPGA and four other PRNG schemes to generate multiple secured keys. Despite its better encryption, the increase in consumption of logic elements (2480) and high-power dissipation (278.65 mW) are viewed as significant drawbacks of this implementation.

Cheng chen et al. [20] designed a Chua circuit based image encryption scheme and implemented in EP4CE15F17C8 FPGA chip. The encryption scheme used 20 ns clock. The chaotic sequences were obtained from the Chua -chaotic system based on the fourth-order Runge- Kutta method, which utilizes more LEs on FPGA. This method produced good randomness when simulated using MATLAB software. In [21], Samar M. Ismail et al. designed a logistic map-based image encryption scheme. The encryption scheme was implemented on Virtex-5 FPGA (Xilinx - XC5VLX50T) and operated at the maximum clock frequency of 58.358 MHz. The encryption scheme was realized using VHDL (Very high speed integrated circuit Hardware Description Language), where the image was stored in the internal RAM of the FPGA. The encryption scheme prototype was implemented with different bus sizes such as 11, 16 and 20-bits. Though the scheme achieves good statistical properties, it suffers due to the lower chaotic span.

A three-layer medical image encryption scheme implemented by padmapriya praveenkumar et al. [22] used Latin Square Image Cipher (LSIC), Discrete Gould Transform (DGT) and Rubik’s encryption. Here, DGT ensured the tamper-proofing, LSIC performed both diffusion and confusion process while Rubik model permutated the DICOM image pixels. This encryption algorithm was simulated under MATLAB software, and its security strength was confirmed with statistical analysis, differential analysis, key sensitivity tests and cropping attack analysis. This scheme offered a larger keyspace and had good resistance against the brute force attacks. However, this scheme requires multiple rounds of operation to yield better encryption quality which affects the throughput. A similar kind of medical image encryption technique was performed by J.B. Lima [23] wherein the scheme utilized the cosine number transform, which has the effect of quantization at decryption. This scheme was designed to encrypt uncompressed DICOM images. Chosen plain text attack analysis, cropping attack analysis and differential attacks analyses were carried out to validate the results.

Concurrency has been emerging as a useful technology in modern computing systems to meet the demand for higher performance with cost-effectiveness for real-time embedded applications. Concurrency aims at handling multiple tasks at the same time. Realizing architectures on reconfigurable hardware such as FPGAs can be supported with concurrency through Hardware Description Language (HDL). This paper’s primary goal is to realize a lightweight Chao-cryptic architecture suitable for concurrent FPGA realization to secure medical images. The features on the use of chaotic keys in crypto architectures are:

Chaotic systems are Non –linear system that brings randomness in its output due to its high sensitivity to initial conditions.

The initial conditions and control parameters of the chaotic architecture can be perturbed in high volume that offers larger keyspace.

The use of chaotic keys offers higher security when utilized in crypto architecture.

Apart from the standard set of security analysis, this paper also analyses the hardware performance of concurrent architectural blocks on FPGA to achieve an optimal tradeoff between the resource utilization, power dissipation and throughput.

2 Preliminaries

2.1 Linear feedback shift register (LFSR)

LFSR is a shift register whose input bit is a linear function of its previous state. The initial value of the LFSR is called the seed [14 , 25]. The LFSR circuit comprises D Flip-Flops with external or internal feedback through Ex-Nor or Ex-Or gates generates distinct values in a pseudo-random order. The tapings of an n-bit LFSR, when chosen adequately for the feedback, ensures the output sequence with the maximum length of 2^n - 1.

2.2 Lorentz chaotic attractor

The sensitive nature of chaotic attractors to their initial conditions and input values makes them highly relevant to generate random numbers used as keys in cryptography applications [5 , 26–31]. The proposed medical image encryption uses the 3 Dimensional Lorentz chaotic attractor to generate keys for the diffusion process. The Equations (1–3) provide the mathematical representation of the 3D Lorentz chaotic attractor [18]. $\frac{dx}{dt} = σ (y - x)$ (1) $\frac{dy}{dt} = - xz + rx - y$ (2) $\frac{dz}{dt} = xy - β z$ (3)

The two-dimensional portraits [26] obtained by implementing the 3D Lorentz system [Equations (1–3)] on MATLAB platform with initial conditions x = 0.1, y = 5.0000000001, z = 25 and control parameters σ = 10, $β = \frac{8}{3}$ and r = 28 are illustrated in Fig. 1.

Fig. 1

Two-dimensional phase portraits of Lorenz chaotic attractor.

3 Proposed methodology

The proposed architecture has four central units, namely block separation, chaotic key generation, PRNG and diffusion unit, that encrypt medical images. A 256×256 DICOM image with 16-bit pixel values has been chosen as input for the proposed algorithm. Initially, the 256×256 input image gets divided into four blocks (B₀ to B₃) of each having 128×128 pixels. Each separated block is then subjected to the diffusion process using the distinct set of keys generated by the Lorentz attractor. The initial and control values for the Lorentz attractor have been taken in IEEE 754 single-precision (32-bit) format to build the chaotic key generation unit.

The first three sets of chaotic keys used to encrypt the blocks B₀ - B₂ is formed from the three output planes of the Lorentz attractor. XORing the Lorenz output from all the three planes produces the key to encrypt the block B₃.

Further, each block’s diffusion process performs an XOR operation between the pixel value and the chaotic key. The resultant diffused image pixels are stored in random addresses of the block RAM generated by an LFSR circuit constructed using the D-FF and XOR gates to induce randomness. Finally, reading the pixels from the block RAM addresses in a sequential order essentially achieves the pixel diffusion that completes the encryption process.

The proposed algorithm has been developed as Verilog HDL code and implemented on reconfigurable hardware, Cyclone IV FPGA (EP4CE115F29C7), Fig. 2 depicts the overall block diagram of the proposed lightweight concurrent architecture for DICOM image encryption. Figure 3a and 3b show the structure of LFSR based confusion key generator circuit and hardware model of the Lorenz chaotic key generator, respectively.

Fig. 2

Block diagram of the proposed medical encryption architecture with 2 ^N concurrent blocks (N = 2).

Fig. 3b

Hardware model of the chaotic key generator (Lorenz attractor).

3.1 Algorithm for encryption

Step 1: Consider a DICOM image of size 256×256 with pixels of 16-bit depth as input.

Step 2: Select a number ‘N’ between 0 to 4 and divide the input DICOM image into 2 ^N non-overlapping blocks of equal size.

Step 3: Considering N = 2, the input image is divided into four blocks of each with size 128 ×128.

Step 4: Run the Lorenz chaotic system given by Equations (1) to (3) with the initial conditions/control parameter values σ= 10, r = 28, β = 8/3, x = 0.1, y = 5.0000000001 and z = 25 and represent the output as binaries using IEEE 754 single-precision format.

Step 5: Obtain the 16-bit diffusion keys by EX-OR ing the three 16-bit values extracted from the LSBs of the binary outputs generated in Step 4.

Step 6: Perform block diffusion by performing XOR operation between every pixel from the block and the 16-bit diffusion key generated in Step 5.

Step 7: Repeat the steps 4 to 6 to concurrently diffuse all the blocks until all the blocks’ pixels get diffused.

Step 8: Select an appropriate primitive polynomial based on the block size chosen in Step 3 to design an LFSR based PRNG circuit.

Step 9: For the chosen block size of 128×128 (N = 2), use the 14-bit LFSR circuit with primitive polynomial (X¹⁴ + X⁵ + X³ + 1) [32] as shown in Fig. 3a to generate random numbers used as confusion keys.

Step 10: Use the confusion key sequence generated in Step 9 as BRAM addresses to instantaneously shuffle the pixel positions inside each diffused block obtained from Step 6.

Step 11: Combine all the confused pixel blocks (128×128 for N = 2) generated from Step 10 to obtain the final encrypted image (256×256).

3.2 Algorithm for decryption

Step 1: Obtain the encrypted image (256×256 with 16-bit pixel depth) from Step 11 of the encryption algorithm.

Step 2: Perform the block splitting by considering N = 2 as given by Steps 2 and 3 of the encryption algorithm.

Step 3: Generate Psuedo-random numbers using 14-bit LFSR circuit given in Steps 8 and 9 of the encryption algorithm.

Step 4: Perform de-shuffling of the encrypted pixels in each 128×128 block (N = 2) by concurrently reading them from BRAM addresses obtained from the LFSR output (Step 3 of the decryption algorithm).

Step 5: Run the Lorenz chaotic system and obtain 16-bit diffusion keys mentioned in Steps 4 and 5 of the encryption algorithm.

Step 6: Perform decryption of pixels from each block obtained from Step 4 as given in Step 4 and 5 of the encryption algorithm.

Step 7: Combine the decrypted pixel blocks (four 128×128 for N = 2) generated from Step 6 of the decryption algorithm to reconstruct the original DICOM image (256×256).

4 Results and discussions

The proposed algorithm used 256×256 grayscale DICOM images as input to analyze its security and performance aspects on cyclone IV FPGA (EP4CE115F29C7). The 16-bit pixels of the DICOM images have been read as a hexadecimal byte stream and loaded in the internal block RAM of FPGA. The pre-processing and post-processing of DICOM images which involves the extraction of pixel values from images and the reconstruction of images from the pixels were carried out using the open-source Python 3.7 on a desktop PC. Security aspects of the proposed scheme have been analyzed with various statistical, randomness tests and keyspace analysis. The proposed architecture’s FPGA performance with varying concurrent crypto blocks has been validated through hardware parameters such as resource utilization, power dissipation and throughput. The ten different DICOM images used for testing and the corresponding encrypted images are shown in Fig. 4a and Fig. 4b, respectively.

Fig. 4b

Encrypted images.

4.1 Security analysis

The list of statistical parameters and metrics for randomness, including PSNR, entropy, correlation, histogram, and NIST, has been analyzed to ensure the proposed algorithm’s competency level to secure DICOM images. Table 1 lists the purpose, critical values for validation, and reference from literature as proof for various statistical metrics used in this section.

Table 1
Metrics for statistical analysis

Metrics Purpose Critical values Proof

Entropy To measure the amount of uncertainty Should be close to ‘n.’ (for images with ‘n’-bit pixel resolution) Ref. [33]

Correlation To measure the ability of the encryption algorithm to break the dependency between the adjacent pixels Should be close to zero Ref. [34]

Histogram To measure the equiprobable distribution of pixel intensity levels Nearly flat-top response in the histogram plot Ref. [1]

PSNR To measure the level of imperceptibility Less than 10 dB Ref. [35]

NIST SP 800-22 To measure the amount of randomness p-value should be >0.001 Ref.[36] & [37]

Metrics	Purpose	Critical values	Proof
Entropy	To measure the amount of uncertainty	Should be close to ‘n.’ (for images with ‘n’-bit pixel resolution)	Ref. [33]
Correlation	To measure the ability of the encryption algorithm to break the dependency between the adjacent pixels	Should be close to zero	Ref. [34]
Histogram	To measure the equiprobable distribution of pixel intensity levels	Nearly flat-top response in the histogram plot	Ref. [1]
PSNR	To measure the level of imperceptibility	Less than 10 dB	Ref. [35]
NIST SP 800-22	To measure the amount of randomness	p-value should be >0.001	Ref.[36] & [37]

4.1.1 Information entropy

Claude Shannon stated a parameter called entropy which is adopted to measure the information quantitatively. As the proposed algorithm takes a 16-bit information source, from Equation (4), the maximum entropy given to obtain uniform probability is 16. Any encrypted image that achieves an entropy value closer to the maximum value is said to have better randomness [33]. The entropy values for various images encrypted through the proposed algorithm with 2 ^N concurrent blocks on FPGA are calculated and tabulated in Table 2. The proposed method achieves lower entropy values for the encrypted images due to the same keys used to encrypt multiple concurrent blocks (when N > 2). Further, the comparison graph for average entropy in Fig. 5 validates the randomness achieved by the proposed concurrent encryption scheme against a similar method for encrypting the 16-bit DICOM image on FPGA.

Table 2
Information entropy for concurrent encryption blocks (2 ^N)

Test Samples Entropy

Original images Encrypted images

N = 0 N = 1 N = 2 N = 3 N = 4

DICOM 1 6.9574 15.1764 15.0256 15.1116 14.6085 14.7791

DICOM 2 7.0882 15.1743 15.0346 15.0215 14.5939 14.7912

DICOM 3 6.5212 15.1779 15.0238 15.0194 14.6073 14.7791

DICOM 4 7.3067 15.1722 15.1385 15.1116 14.5805 14.9447

DICOM 5 7.0899 15.1727 15.0253 15.0180 14.5887 14.7830

DICOM 6 6.8876 15.1774 15.1561 15.1514 15.0033 14.8560

DICOM 7 7.1227 15.1548 15.1563 15.1548 15.0078 14.7452

DICOM 8 6.9980 15.1774 15.1659 15.1621 15.0065 14.7022

DICOM 9 7.1187 15.1775 15.1766 15.1264 15.0066 14.7108

DICOM 10 7.2560 15.1725 15.1355 15.0988 15.0081 14.7112

Test Samples	Entropy
DICOM 1	6.9574	15.1764	15.0256	15.1116	14.6085	14.7791
DICOM 2	7.0882	15.1743	15.0346	15.0215	14.5939	14.7912
DICOM 3	6.5212	15.1779	15.0238	15.0194	14.6073	14.7791
DICOM 4	7.3067	15.1722	15.1385	15.1116	14.5805	14.9447
DICOM 5	7.0899	15.1727	15.0253	15.0180	14.5887	14.7830
DICOM 6	6.8876	15.1774	15.1561	15.1514	15.0033	14.8560
DICOM 7	7.1227	15.1548	15.1563	15.1548	15.0078	14.7452
DICOM 8	6.9980	15.1774	15.1659	15.1621	15.0065	14.7022
DICOM 9	7.1187	15.1775	15.1766	15.1264	15.0066	14.7108
DICOM 10	7.2560	15.1725	15.1355	15.0988	15.0081	14.7112

Fig. 5

Comparison on average entropy of encrypted images.

In any grayscale image having m-bit pixel values, the maximum pixel intensity value is given by 2^m - 1. In Equation (4), P_i is the probability of the grayscale intensity level ‘i’ in the image. Entropy,

$H (m) = - \sum_{i = 1}^{n} p_{i} \times {log}_{2} p_{i}$ (4)

4.1.2 Histogram analysis

The histogram plots the number of pixels at each intensity level to give a visual form of interpretation for the pixel distribution in images [1]. Figure 6a depicts a histogram of original images. As shown in Fig. 6b –6d, the histogram plot for the images encrypted with the proposed concurrent approach with N = 0 to 4 gives nearly flat top that implies the equal number of occurrences of all pixels intensity levels.

Fig. 6d

Histogram of Encrypted Images (N = 4).

4.1.3 Correlation coefficient analysis

The correlation coefficient is one of the fundamental metrics to evaluate the strength of an encrypted image. The lower value of correlation coefficients in horizontal, vertical and diagonal axes of an encrypted image indicates the encryption algorithm’s ability to break the adjacent pixels’ dependency [34]. As the adjacent pixels in any DICOM image are highly correlated, it requires an efficient encryption mechanism to provide near-zero or negative correlation. The correlation values obtained from Equation (5) for the original and encrypted images are plotted in Figs. 7 and 8, respectively. Correlation,

Fig. 7

Correlation graph for the original image (DICOM 1).

Fig. 8

Correlation analysis for encrypted image (DICOM 1) with (2 ^N) concurrent blocks.

$ρ_{xy} = \frac{cov (x, y)}{σ_{x} σ_{y}}$ (5)

Where x and y are grayscale values of two adjacent pixels in the image. σ_x and σ_y are the Standard deviation of (x, y). cov (x, y) is the covariance of (x, y).

4.1.4 PSNR analysis

In image encryption, PSNR gives the ratio between the peak signal and noise power between the original image and its encrypted form [35]. The Mean Square Error (MSE) in Equation (6) is involved in the estimation of PSNR value as given by the Equation (7). The image encryption algorithm that achieves a low PSNR value (<10 dB) maximizes the difference between plain and encrypted image. The PSNR values estimated from Equation (7) for the proposed concurrent image encryption scheme are listed in Table 3. The PSNR value of <5 dB shown in the average PSNR comparison graph in Fig. 9 confirms the proposed scheme’s strength against the one available in the literature [35].

Table 3
PSNR analysis

Test samples PSNR(dB)

No of concurrent blocks(2 ^N)

N = 0 N = 1 N = 2 N = 3 N = 4

DICOM 1 4.7968 4.8043 4.8002 4.9933 4.7967

DICOM 2 4.7972 4.7168 4.7955 4.9852 4.7168

DICOM 3 4.7874 4.7945 4.7853 4.9753 4.7061

DICOM 4 4.8046 4.8124 4.9933 4.9933 4.7235

DICOM 5 4.8031 4.8104 4..9914 4.9914 4.7228

DICOM 6 4.8066 4.8565 4.8700 4.9056 4.9920

DICOM 7 4.6558 4.7235 4.8845 4.8890 4.9876

DICOM 8 4.6778 4.6890 4.8122 4.8905 4.9905

DICOM 9 4.5764 4.7805 4.7990 4.8650 4.9920

DICOM 10 4.5890 4.6783 4.7782 4.8509 4.8885

Test samples	PSNR(dB)
DICOM 1	4.7968	4.8043	4.8002	4.9933	4.7967
DICOM 2	4.7972	4.7168	4.7955	4.9852	4.7168
DICOM 3	4.7874	4.7945	4.7853	4.9753	4.7061
DICOM 4	4.8046	4.8124	4.9933	4.9933	4.7235
DICOM 5	4.8031	4.8104	4..9914	4.9914	4.7228
DICOM 6	4.8066	4.8565	4.8700	4.9056	4.9920
DICOM 7	4.6558	4.7235	4.8845	4.8890	4.9876
DICOM 8	4.6778	4.6890	4.8122	4.8905	4.9905
DICOM 9	4.5764	4.7805	4.7990	4.8650	4.9920
DICOM 10	4.5890	4.6783	4.7782	4.8509	4.8885

Fig. 9

Comparison of average PSNR values.

$MSE = \frac{1}{M \times N} \sum_{i = 0}^{M - 1} \sum_{j = 0}^{N - 1} (I_{ij} - C_{ij})^{2}$ (6) $PSNR = 1 - {log}_{10} (\frac{1}{MSE})$ (7)

In an image with M rows and N columns, I_ij & C_ij represent a pixel from the original and cipher image respectively with row, column position given by (i,j).

4.2 Keyspace analysis

Larger keyspace provides high security and helps the encryption algorithm resist brute force attack [8, 30]. The confusion and diffusion unit of the proposed image encryption scheme uses distinct keys. In an implementation with 2 ^N concurrent blocks; the confusion unit uses 2 ^N independent LFSRs with different seed values to arrive at unique random keys to confuse each block’s pixels. The length of the LFSR circuit gets determined according to the block size. Considering the input image of size 256×256 and number of concurrent blocks as 4 (N = 2 makes the block size as 128×128), four independent LFSRs (2 ^N) each with a length of 14-bit is used. Thus, LFSR’s keyspace for confusion becomes larger when multiple concurrent blocks are used (2¹⁴×4 for N = 2). The diffusion unit’s key gets generated from the Lorentz attractor described in section 1.2.2, which uses six float variables as inputs in the form of initial conditions and constants. As each of these float variables is represented in 32-bit IEEE 754 format when implemented on the FPGA hardware, the diffusion keyspace becomes 2³²×6, independent of the number of concurrent blocks used.

The linear increase in the keyspace achieved on combining the keys from confusion and diffusion units based on the number of concurrent architectural blocks used are tabulated in Table 4. The proposed architecture achieves the maximum keyspace of 2³⁸⁴ (with N = 4) guarantees larger keyspace against the similar image encryption schemes reported in the literature are tabulated in Table 5.

Table 4
Keyspace analysis for concurrent blocks

Number of concurrent blocks (2 ^N) N = 0 N = 1 N = 2 N = 3 N = 4

key space 2²⁰⁸ 2²²⁴ 2²⁴⁸ 2²⁹⁶ 2³⁸⁴

Number of concurrent blocks (2 ^N)	N = 0	N = 1	N = 2	N = 3	N = 4
key space	2²⁰⁸	2²²⁴	2²⁴⁸	2²⁹⁶	2³⁸⁴

Table 5

Comparison of the keyspace

Encryption Scheme	Image Size &Type	Key Space
Proposed	256×256 DICOM	2³⁸⁴
Ref. [19]	256×256 DICOM	2³⁴⁵
Ref. [38]	256×256 RGB	2¹⁶⁸
Ref. [7]	256×256 RGB	2²²⁴

4.3 Randomness test for encrypted images using NIST test suite

NIST SP 800-22 provides a set of useful procedures to ensure the randomness in a binary sequence [36, 37]. In the proposed concurrent architecture, the encrypted DICOM images’ pixel values reside in the on-chip RAM of cyclone IV FPGA. These encrypted pixel values are converted into a binary bitstream after extraction and subjected to various statistical randomness tests under the NIST SP 800-22 test suite.

The minimum pass rate for each statistical test except for the random excursion (variant) test is P ≈ 8 for a binary block size of 10. The NIST SP 800-22 test report obtained on evaluating the pixels’ randomness in the encrypted image (DICOM 1) obtained from the proposed scheme is presented in Table 6. The NIST SP 800-22 evaluation report for all input DICOM images encrypted with the different number of concurrent blocks (2 ^N) with p-value ensures the cipher images’ randomness resulted from the proposed concurrent image encryption architecture.

Table 6
Randomness evaluation of encrypted image (DICOM 1) under NIST SP 800-22

NIST SP 800-22 Test Number of concurrent blocks (2 ^N)

N = 0 N = 1 N = 2 N = 3 N = 4

P Pr P Pr P Pr P Pr P Pr

Frequency 10 0.739918 9 0.911413 10 0.534146 8 0.534146 10 0.213309

Block frequency 9 0.213309 9 0.350485 9 0.534146 8 0.213309 9 0.739918

Cumulative Sums I 19 0.534146 9 0.739918 9 0.911413 8 0.350485 9 0.911413

Cumulative Sums II 10 0.350485 9 0.534146 9 0.534146 9 0.739918 10 0.350485

Runs 10 0.534146 9 0.017912 10 0.911413 9 0.739918 9 0.035174

Longest Run 10 0.122325 10 0.911413 10 0.350485 10 0.350485 10 0.122325

Rank 10 0.004301 10 0.122325 10 0.350485 10 0.739918 10 0.739918

FFT 10 0.350485 10 0.739918 10 0.739918 10 0.213309 10 0.911413

Non-overlapping Template 10 0.350485 10 0.534146 10 0.534146 10 0.350485 9 0.066882

Overlapping Template 10 0.534146 10 0.534146 10 0.350485 10 0.066882 9 0.213309

Approximate Entropy 10 0.350485 9 0.122325 9 0.739918 9 0.739918 9 0.350485

Serial –I 9 0.911413 9 0.739918 9 0.066882 9 0.213309 9 0.739918

Serial –II 9 0.911413 8 0.350485 8 0.066882 9 0.534146 9 0.534146

Linear Complexity 8 0.350485 10 0.739918 8 0.350485 10 0.122325 8 0.739918

NIST SP 800-22 Test	Number of concurrent blocks (2 ^N)
Frequency	10	0.739918	9	0.911413	10	0.534146	8	0.534146	10	0.213309
Block frequency	9	0.213309	9	0.350485	9	0.534146	8	0.213309	9	0.739918
Cumulative Sums I	19	0.534146	9	0.739918	9	0.911413	8	0.350485	9	0.911413
Cumulative Sums II	10	0.350485	9	0.534146	9	0.534146	9	0.739918	10	0.350485
Runs	10	0.534146	9	0.017912	10	0.911413	9	0.739918	9	0.035174
Longest Run	10	0.122325	10	0.911413	10	0.350485	10	0.350485	10	0.122325
Rank	10	0.004301	10	0.122325	10	0.350485	10	0.739918	10	0.739918
FFT	10	0.350485	10	0.739918	10	0.739918	10	0.213309	10	0.911413
Non-overlapping Template	10	0.350485	10	0.534146	10	0.534146	10	0.350485	9	0.066882
Overlapping Template	10	0.534146	10	0.534146	10	0.350485	10	0.066882	9	0.213309
Approximate Entropy	10	0.350485	9	0.122325	9	0.739918	9	0.739918	9	0.350485
Serial –I	9	0.911413	9	0.739918	9	0.066882	9	0.213309	9	0.739918
Serial –II	9	0.911413	8	0.350485	8	0.066882	9	0.534146	9	0.534146
Linear Complexity	8	0.350485	10	0.739918	8	0.350485	10	0.122325	8	0.739918

5 Hardware implementation analysis

The proposed medical image encryption scheme realized as Verilog HDL (Hardware Description Language) code, synthesized through Quartus II IDE (Integrated Development Environment) and implemented on Cyclone IV FPGA. The major on-chip features of EP4CE115F29C7 FPGA utilized in this implementation includes the 114,480 Logic Elements (LEs), 432M9K memory blocks, 3,888 Kbits of embedded memory and 4 PLL’s (Phase Locked Loop).

The snapshot of internal block RAM in cyclone IV FPGA containing a part of image pixels (DICOM1) encrypted by the proposed concurrent architecture (N = 2) has been shown in Fig. 10. The Section of Register Transfer Level (RTL) schematic in Figs. 11 and 12 depicts the abstract design of the data flow between the hardware registers for the confusion and diffusion units in the proposed implementation.

Fig. 10

Snapshot of internal Block RAM in cyclone IV FPGA with encrypted pixels.

Fig. 11

A Section of RTL View - Confusion unit.

Fig. 12

A Section of RTL view - Diffusion unit.

5.1 Resource utilization analysis

Table 7 presents the HDL code’s synthesis report for the proposed encryption scheme listing the rise in the utilization of various resources against multiple concurrent blocks. Table 8 compares the resource utilization by the similar image encryption schemes implemented on cyclone II FPGA with the proposed scheme implemented on Cyclone IV FPGA.

Table 7
Resource utilization analysis for concurrent blocks

Test samples Hardware parameters N = 0 N = 1 N = 2 N = 3 N = 4

DICOM 1 Logic Elements 1005 1021 1247 1804 3014

Combinational functions 854 877 1005 1529 2545

Logic registers 547 581 804 1199 2066

Memory (bits) 1,96,6080 1,703,936 1,703,936 1,703,936 1,703,936

DICOM 2 Logic Elements 1007 1073 1251 1797 3009

Combinational functions 858 879 1009 1531 3009

Logic registers 547 581 804 1199 2066

Memory (bits) 1,703,936 1,703,936 1,703,936 1,703,936 1,703,936

DICOM 3 Logic Elements 1007 1022 1247 1788 2972

Combinational functions 858 879 1009 1531 2546

Logic registers 547 581 804 1189 2024

Memory (bits) 1,703,936 1,703,936 1,703,936 1,703,936 1,703,936

DICOM 4 Logic Elements 926 1037 1268 1802 2987

Combinational functions 748 897 1017 1534 2532

Logic registers 547 581 820 1199 2049

Memory (bits) 1,703,936 1,703,936 1,703,936 1,703,936 1,703,936

DICOM 5 Logic Elements 873 1024 1246 1800 3012

Combinational functions 734 880 1006 1531 2545

Logic registers 547 593 804 1199 2065

Memory (bits) 1,703,936 1,703,936 1,703,936 1,703,936 1,703,936

DICOM 6 Logic Elements 810 956 1226 1772 2875

Combinational functions 679 710 1002 1517 2480

Logic registers 425 572 784 1172 1998

Memory (bits) 1,048,576 1,572,864 1,572,864 1,572,864 1,572,864

DICOM 7 Logic Elements 808 953 1225 1770 2878

Combinational functions 677 707 1000 1515 2468

Logic registers 425 572 784 1172 1998

Memory (bits) 1,048,576 1,572,864 1,572,864 1,572,864 1,572,864

DICOM 8 Logic Elements 812 958 1229 1773 2890

Combinational functions 679 712 1004 1522 2450

Logic registers 425 572 784 1172 1998

Memory (bits) 1,048,576 1,572,864 1,572,864 1,572,864 1,572,864

DICOM 9 Logic Elements 809 948 1225 1770 2894

Combinational functions 676 704 1000 1515 2447

Logic registers 425 572 784 1172 1998

Memory (bits) 1,048,576 1,572,864 1,572,864 1,572,864 1,572,864

DICOM 10 Logic Elements 806 940 1225 1774 2998

Combinational functions 673 698 999 1519 2450

Logic registers 425 572 784 1172 1998

Memory (bits) 1,048,576 1,572,864 1,572,864 1,572,864 1,572,864

Test samples	Hardware parameters	N = 0	N = 1	N = 2	N = 3	N = 4
DICOM 1	Logic Elements	1005	1021	1247	1804	3014
	Combinational functions	854	877	1005	1529	2545
	Logic registers	547	581	804	1199	2066
	Memory (bits)	1,96,6080	1,703,936	1,703,936	1,703,936	1,703,936
DICOM 2	Logic Elements	1007	1073	1251	1797	3009
	Combinational functions	858	879	1009	1531	3009
	Logic registers	547	581	804	1199	2066
	Memory (bits)	1,703,936	1,703,936	1,703,936	1,703,936	1,703,936
DICOM 3	Logic Elements	1007	1022	1247	1788	2972
	Combinational functions	858	879	1009	1531	2546
	Logic registers	547	581	804	1189	2024
	Memory (bits)	1,703,936	1,703,936	1,703,936	1,703,936	1,703,936
DICOM 4	Logic Elements	926	1037	1268	1802	2987
	Combinational functions	748	897	1017	1534	2532
	Logic registers	547	581	820	1199	2049
	Memory (bits)	1,703,936	1,703,936	1,703,936	1,703,936	1,703,936
DICOM 5	Logic Elements	873	1024	1246	1800	3012
	Combinational functions	734	880	1006	1531	2545
	Logic registers	547	593	804	1199	2065
	Memory (bits)	1,703,936	1,703,936	1,703,936	1,703,936	1,703,936
DICOM 6	Logic Elements	810	956	1226	1772	2875
	Combinational functions	679	710	1002	1517	2480
	Logic registers	425	572	784	1172	1998
	Memory (bits)	1,048,576	1,572,864	1,572,864	1,572,864	1,572,864
DICOM 7	Logic Elements	808	953	1225	1770	2878
	Combinational functions	677	707	1000	1515	2468
	Logic registers	425	572	784	1172	1998
	Memory (bits)	1,048,576	1,572,864	1,572,864	1,572,864	1,572,864
DICOM 8	Logic Elements	812	958	1229	1773	2890
	Combinational functions	679	712	1004	1522	2450
	Logic registers	425	572	784	1172	1998
	Memory (bits)	1,048,576	1,572,864	1,572,864	1,572,864	1,572,864
DICOM 9	Logic Elements	809	948	1225	1770	2894
	Combinational functions	676	704	1000	1515	2447
	Logic registers	425	572	784	1172	1998
	Memory (bits)	1,048,576	1,572,864	1,572,864	1,572,864	1,572,864
DICOM 10	Logic Elements	806	940	1225	1774	2998
	Combinational functions	673	698	999	1519	2450
	Logic registers	425	572	784	1172	1998
	Memory (bits)	1,048,576	1,572,864	1,572,864	1,572,864	1,572,864

Table 8

Resource utilisation comparison

Encryption Scheme	FPGA	Image	No of LUTs	No of Registers	No of Logic elements	Total number of embedded Multipliers
Proposed	Cyclone IV	256×256 DICOM	1006	840	1,284	26
Ref [39]	Cyclone II	128×128 DICOM	–	–	12,929	–
Ref [19]		256×256 DICOM	2422	702	2480	10

5.2 Power dissipation analysis

The amount of power dissipated by any FPGA hardware gets influenced by the factors such as device switching speed, memory utilization and operations concerned with the algorithm implemented. The total power dissipation can be expressed [19] as, Fig. 13 analyses the various kind of power dissipation for the proposed concurrent architecture. It can be observed from Fig. 13 that, the amount of static and I/O power dissipation remains constant irrespective of the number of concurrent blocks used.

Fig. 13

Power Dissipation Comparison for (2 ^N) concurrent blocks.

Conversely, a slight increase in the dynamic power dissipation is detected using more concurrent blocks resulting from the rise in the consumption of logic elements. On referring the Table 9, it is evident that the maximal total power dissipation measured for the proposed scheme with the highest number of concurrent blocks (16 for N = 4) is significantly lower than the earlier image encryption implementations on FPGA.

Table 9

Power dissipation comparison

Encryption Scheme	FPGA	Power dissipation (mW)
Proposed	Cyclone IV	145.08
Ref [19]	Cyclone II	278.65
Ref [38]	Cyclone II	210.00
Ref [39]	Cyclone II	344.91

Total thermal power dissipation = Static power dissipation + Dynamic power dissipation + I/O power dissipation

5.3 Performance analysis

For a DICOM image of size 256×256 with 16-bit depth pixel values as input, incorporating concurrency on the proposed image encryption architecture enhances the system throughput. Independent of the input DICOM image (with identical sizes) the proposed architecture offers a throughput of 159.84 Mbps without concurrency (2^N = 1) when the Cyclone IV FPGA was operated at a frequency of 50 MHz. Based on the inference from Table 10, the throughput offered by proposed encryption architecture approximately gets multiplied by a factor of 2 ^N against the one obtained without concurrency.

Table 10
Time vs Throughput

Number of blocks (2 ^N) Time Throughput

0 6.56 ms 159.84 Mbps

1 3.2 ms 327.68 Mbps

2 1.6 ms 639.37 Mbps

3 800 us 1.31 Gbps

4 400 us 2.62 Gbps

Number of blocks (2 ^N)	Time	Throughput
0	6.56 ms	159.84 Mbps
1	3.2 ms	327.68 Mbps
2	1.6 ms	639.37 Mbps
3	800 us	1.31 Gbps
4	400 us	2.62 Gbps

The computational time has been captured by interfacing the ZEROPLUS logic analyzer with the FPGA board. The screenshot of the same is shown in Fig. 14.

Fig. 14

Timing analysis for N = 2.

6 Conclusion

This paper presented a lightweight Chao-cryptic architecture that supports concurrent realization on FPGA to secure grayscale medical images. Each pixel of the input image undergoes an instantaneous diffusion with a chaotic key from the Lorenz attractor. The diffused pixels gets confused inline during their storage in the on-chip block RAM of the chosen FPGA at the pseudo-random addresses generated from an LFSR. With its larger keyspace of 2³⁸⁴, the proposed concurrent architecture achieves an average PSNR of below 5 dB with the disparate relationship among the encrypted images’ pixels though its strong diffusion and confusion processes. The various numbers of concurrent architectures (2 ^N with N = 0 to 4), consuming less than 3% of its total LEs when implemented on Cyclone IV FPGA (EP4CE115F29C7) substantiates the lightweight property of the algorithm. It was inferred that the proposed encryption scheme achieves a higher throughput of around 160 Mbps per concurrent block with an approximate rise in the utilization of logic elements by 20%. Further, degradation on encryption quality was observed in terms of low entropy values of the encrypted images with the number of concurrent architectural blocks (2 ^N) on FPGA being more than 4 (with N > 2). Unlike similar works reported in the literature, the proposed scheme achieves optimality through good encryption with higher throughput (639.37 Mbps), low power dissipation (138.85 mW) and minimal resource utilization (1268 LEs) when the number of concurrent architectural blocks on FPGA is limited to 4 (N = 2). The future work will reduce dynamic power dissipation in the larger off-chip memory of FPGA to support the encryption of larger grayscale images and colour images.

Footnotes

Acknowledgments

Authors thank Department of Science & Technology, New Delhi for the FIST funding (SR/FST/ET-II/2018/221). Also, Authors wish to thank the Intrusion Detection Lab at School of Electrical & Electronics Engineering, SASTRA Deemed University for providing infrastructural support to carry out this research work.

References

, Liu

and Liu

, Novel image encryption algorithm based on improved logistic map, IET Image Process 13(1) (2018), 125–134. DOI: 10.1049/iet-ipr.2018.5900

Cosman

P.C.

, Gray

R.M.

and Olshen

R.A.

, Evaluating Quality of Compressed Medical Images: SNR, Subjective Rating, and Diagnostic Accuracy, Proc IEEE 82(6) (1994), 919–932. DOI: 10.1109/5.286196

Wong

, Huang

H.K.

, Zaremba

and Gooden

, Radiologic Image Compression—A Review, Proc IEEE 83(2) (1995), 194–219. DOI: 10.1109/5.364466

Rosslyn

, DICOMPS 3.15 Security and System Management Profiles, DICOM Stand (2011).

Rajagopalan

, Rethinam

, Arumugham

, Upadhyay

H.N.

, Rayappan

J.B.B.

and Amirtharajan

, Networked hardware assisted key image and chaotic attractors for secure RGB image communication, Multimedia Tools and Applications 77(18) (2018).

Rajagopalan

, Sivaraman

, Upadhyay

H.N.

, Rayappan

J.B.B.

and Amirtharajan

, ON–Chip peripherals are ON for chaos –an image fused encryption, 257–278, Microprocess. Microsyst. 61 (2017), 2018–10.1016/j.micpro.2018.06.011

Ramalingam

, Ravichandran

, Annadurai

A.A.

, Rengarajan

and Rayappan

J.B.B.

, Chaos triggered image encryption - a reconfigurable security solution, Multimed Tools Appl 77(10) (2018), 11669–11692. DOI: 10.1007/s11042-017-4811-x

Praveenkumar

, et al., Transreceiving of encrypted medical image –a cognitive approach, Multimed Tools Appl 77(7) (2018), 8393–8418. DOI: 10.1007/s11042-017-4741-7

Ramírez-Torres

M.T.

, Murguía

J.S.

and Carlos

M.M.

, Image encryption with an improved cryptosystem based on a matrix approach, Int J Mod Phys C 25(10) (2014), 1450054–10.1142/s0129183114500545

10.

, et al., An efficient and secure medical image protection scheme based on chaotic maps, Comput Biol Med 43(8) (2013), 1000–1010. DOI: 10.1016/j.compbiomed.2013.05.005

11.

Ravichandran

, Praveenkumar

, Rayappan

J.B.B.

and Amirtharajan

, DNA Chaos Blend to Secure Medical Privacy, IEEE Trans Nanobioscience 16(8) (2017), 850–858. DOI: 10.1109/TNB.2017.2780881

12.

Cao

, Zhou

, Chen

C.L.P.

and Xia

, Medical image encryption using edge maps, Signal Processing 132 (2017), 96–109. DOI: 10.1016/j.sigpro.2016.10.003

13.

Chandrasekaran

and Thiruvengadam

S.J.

, A hybrid chaotic and number theoretic approach for securing DICOM images, Secur Commun Networks 2017 (2017)–10.1155/2017/6729896

14.

Belazi

, Talha

, Kharbech

and Xiang

, Novel Medical Image Encryption Scheme Based on Chaos and DNA Encoding, IEEE Access 7 (2019), 36667–36681. DOI: 10.1109/ACCESS.2019.2906292

15.

Abdellatif

K.M.

, Chotin-Avot

and Mehrez

, Authenticated encryption on FPGAs from the static part to the reconfigurable part, Microprocess Microsyst 38(6) (2014), 526–538. DOI: 10.1016/j.micpro.2014.03.006

16.

Janakiraman

, Thenmozhi

, Rayappan

J.B.B.

and Amirtharajan

, Lightweight chaotic image encryption algorithm for real-time embedded system: Implementation and analysis on 32-bit microcontroller, Microprocess Microsyst (2018). DOI:10.1016/j.micpro.2017.10.013

17.

Siva Janakiraman

R.A.

and Rajagopalan

, Reliable Medical Image Communication in Healthcare IoT: Watermark for Authentication, i (2019).

18.

Sundararaman Rajagopalan

R.A.

and Janakiraman

, Medical Image Encryption: Microcontroller and FPGA Perspective, i (2019)–10.4018/978-1-5225-7952-6.ch003

19.

Ravichandran

, Rajagopalan

, Upadhyay

H.N.

, Rayappan

J.B.B.

and Amirtharajan

, Encrypted Biography of Biomedical Image - a Pentalayer Cryptosystem on FPGA, J Signal Process Syst 91(5) (2019), 475–501. DOI: 10.1007/s11265-018-1337-z

20.

Chen

, Ma

, Chen

, Meng

and Ding

, FPGA implementation of a UPT chaotic signal generator for image encryption, Pacific Sci Rev A Nat Sci Eng 17(3) (2015), 97–102. DOI: 10.1016/j.psra.2016.02.001

21.

Ismail

S.M.

, et al., Generalized fractional logistic map encryption system based on FPGA, AEU - Int J Electron Commun 80 (2017), 114–126. DOI: 10.1016/j.aeue.2017.05.047

22.

Praveenkumar

, Amirtharajan

, Thenmozhi

and Balaguru Rayappan

J.B.

, Medical data sheet in safe havens - A tri-layer cryptic solution, Comput Biol Med 62 (2015), 264–276. DOI: 10.1016/j.compbiomed.2015.04.031

23.

Lima

J.B.

, Madeiro

and Sales

F.J.R.

, Encryption of medical images based on the cosine number transform, Signal Process Image Commun 35 (2015), 1–8. DOI: 10.1016/j.image.2015.03.005

24.

Tong

X.J.

, The novel bilateral - Diffusion image encryption algorithm with dynamical compound chaos, J Syst Softw 85(4) (2012), 850–858. DOI: 10.1016/j.jss.2011.10.051

25.

Raj

, Janakiraman

, Rajagopalan

and Rengarajan

, Confused Memory Read Attracts Synthetic Diffusion on the Fly – A Lightweight Image Encryption for IoT Platform, in Applications and Techniques in Information Security (2019), 62–73.

26.

Yang

C.H.

, Wu

H.C.

and Su

S.F.

, Implementation of Encryption Algorithm and Wireless Image Transmission System on FPGA,3–3, IEEE Access 7 (2019)–10.1109/ACCESS.2019.2910859

27.

Merah

, Ali-Pacha

, Said

N.H.

and Mamat

, Design and FPGA implementation of Lorenz chaotic system for information security issues, Appl Math Sci 7(5) (2016), 237–246. DOI: 10.12988/ams.2013.13022

28.

Kyrkou

and Theocharides

, A flexible parallel hardware architecture for AdaBoost-based real-time object detection, IEEE Trans Very Large Scale Integr Syst 19(6) (2011), 1034–1047. DOI: 10.1109/TVLSI.2010.2048224

29.

Nagar

, Prasad Mohapatra

and Chaki

, Proceedings of 3rd International Conference on Advanced Computing, Networking and Informatics: ICACNI Volume 1, Smart Innov Syst Technol 43 (2016), 227–237. DOI: 10.1007/978-81-322-2538-6

30.

Pareek

N.K.

and Patidar

, Medical image protection using genetic algorithm operations, Soft Comput 20(2) (2016), 763–772. DOI: 10.1007/s00500-014-1539-7

31.

Senouci

, Bouhedjeur

, Tourche

and Boukabou

, FPGA based hardware and device-independent implementation of chaotic generators, AEU - Int J Electron Commun 82 (2017), 211–220. DOI: 10.1016/j.aeue.2017.08.011

32.

Alfke

, Efficient Shift Registers, LFSR Counters, and Long Pseudo- Random Sequence Generators, Xilinx 1996 (1996), 1–6. DOI: 10.1016/S0924-0136(02)00796-3

33.

Arumugham

, Rajagopalan

, Rayappan

J.B.B.

and Amirtharajan

, Tamper-Resistant Secure Medical Image Carrier: An IWT–SVD–Chaos–FPGA Combination, Arab J Sci Eng 44(11) (2019), 9561–9580. DOI: 10.1007/s13369-019-03883-x

34.

Ravichandran

, Praveenkumar

, Balaguru Rayappan

J.B.

and Amirtharajan

, Chaos based crossover and mutation for securing DICOM image, Comput Biol Med 72 (2016), 170–184. DOI: 10.1016/j.compbiomed.2016.03.020

35.

Laiphrakpam

D.S.

and Khumanthem

M.S.

, Medical image encryption based on improved ElGamal encryption technique, Optik (Stuttg) 147 (2017), 88–102. DOI: 10.1016/j.ijleo.2017.08.028

36.

Sivaraman

, Rajagopalan

, Sridevi

, Rayappan

J.B.B.

, Annamalai

M.P.V.

and Rengarajan

, Metastability-Induced TRNG Architecture on FPGA, Iran J Sci Technol - Trans Electr Eng 2 (2019)–10.1007/s40998-019-00234-2

37.

Devi

R.S.

, Thenmozhi

, Rayappan

J.B.B.

, Amirtharajan

and Praveenkumar

, Entropy Influenced RNA Diffused Quantum Chaos to Conserve Medical Data Privacy, Int J Theor Phys (2019), 1937–1956. DOI:10.1007/s10773-019-04088-6

38.

Ramalingam

, Rengarajan

and Rayappan

J.B.B.

, Hybrid image crypto system for secure image communication–A VLSI approach, Microprocess Microsyst 50 (2017), 1–13. DOI: 10.1016/j.micpro.2017.02.003

39.

Rajagopalan

, Dhamodaran

, Ramji

, Francis

, Venkatraman

and Amirtharajan

, Confusion and diffusion onFPGA- Onchip solution for medical image security, 2017 Int Conf Comput Commun Informatics ICCCI 2017, (2017), DOI:10.1109/ICCCI.2017.8117770

Test Samples	Entropy
	Original images	Encrypted images
		N = 0	N = 1	N = 2	N = 3	N = 4
DICOM 1	6.9574	15.1764	15.0256	15.1116	14.6085	14.7791
DICOM 2	7.0882	15.1743	15.0346	15.0215	14.5939	14.7912
DICOM 3	6.5212	15.1779	15.0238	15.0194	14.6073	14.7791
DICOM 4	7.3067	15.1722	15.1385	15.1116	14.5805	14.9447
DICOM 5	7.0899	15.1727	15.0253	15.0180	14.5887	14.7830
DICOM 6	6.8876	15.1774	15.1561	15.1514	15.0033	14.8560
DICOM 7	7.1227	15.1548	15.1563	15.1548	15.0078	14.7452
DICOM 8	6.9980	15.1774	15.1659	15.1621	15.0065	14.7022
DICOM 9	7.1187	15.1775	15.1766	15.1264	15.0066	14.7108
DICOM 10	7.2560	15.1725	15.1355	15.0988	15.0081	14.7112

Test samples	PSNR(dB)
	No of concurrent blocks(2 ^N)
	N = 0	N = 1	N = 2	N = 3	N = 4
DICOM 1	4.7968	4.8043	4.8002	4.9933	4.7967
DICOM 2	4.7972	4.7168	4.7955	4.9852	4.7168
DICOM 3	4.7874	4.7945	4.7853	4.9753	4.7061
DICOM 4	4.8046	4.8124	4.9933	4.9933	4.7235
DICOM 5	4.8031	4.8104	4..9914	4.9914	4.7228
DICOM 6	4.8066	4.8565	4.8700	4.9056	4.9920
DICOM 7	4.6558	4.7235	4.8845	4.8890	4.9876
DICOM 8	4.6778	4.6890	4.8122	4.8905	4.9905
DICOM 9	4.5764	4.7805	4.7990	4.8650	4.9920
DICOM 10	4.5890	4.6783	4.7782	4.8509	4.8885

Optimal concurrency on FPGA for lightweight medical image encryption

Abstract

Keywords

1 Introduction

2 Preliminaries

2.1 Linear feedback shift register (LFSR)

2.2 Lorentz chaotic attractor

3.2 Algorithm for decryption

4 Results and discussions

Table 4 Keyspace analysis for concurrent blocks Number of concurrent blocks (2 N) N = 0 N = 1 N = 2 N = 3 N = 4 key space 2208 2224 2248 2296 2384

Table 10 Time vs Throughput Number of blocks (2 N) Time Throughput 0 6.56 ms 159.84 Mbps 1 3.2 ms 327.68 Mbps 2 1.6 ms 639.37 Mbps 3 800 us 1.31 Gbps 4 400 us 2.62 Gbps

Footnotes

Acknowledgments

References

Table 4
Keyspace analysis for concurrent blocks

Number of concurrent blocks (2 ^N) N = 0 N = 1 N = 2 N = 3 N = 4

key space 2²⁰⁸ 2²²⁴ 2²⁴⁸ 2²⁹⁶ 2³⁸⁴

Table 10
Time vs Throughput

Number of blocks (2 ^N) Time Throughput

0 6.56 ms 159.84 Mbps

1 3.2 ms 327.68 Mbps

2 1.6 ms 639.37 Mbps

3 800 us 1.31 Gbps

4 400 us 2.62 Gbps