MOS capacitor based Dickson charge pump and ripple cancellation techniques using an LC circuit

Abstract

This paper proposes a new architecture using integrated inductor and MOS capacitor based on Dickson charge pump associated with two parallel LC circuit after the first stage and output stage which cancel the ripple voltage that is generated in the output stage. In this circuit, the MOS capacitor as used instead of pumping capacitor, which helps in reducing the circuit Silicon area. Efficiency up to 80–90% can be achieved by reducing the parasitic effects and by using a MOS capacitor. The efficiency conversion and voltage gain increase or decreases depending on inductor and capacitor values. Vt drop loss is managed using high voltage clock. It shows that 3.5 V output voltage is generated from input voltage of 1.0 V with five stages of MOS capacitor (used as Pumping capacitor) in working frequency of 100 MHz the simulations were performed in Cadence Virtuoso platform with 0.18 $\mu$ m CMOS process.

Keywords

MOS capacitor LC circuits non-overlapping clock generator capacitive divider circuit

1. Introduction

The charge pump (CP) and boost converter circuits are a category of switched-capacitor (DC to DC) which works on two-phase clock voltage. The primary boost converter circuit is shown in Fig. 1. It is used for small electronic devices which run on battery and requires low voltage. The power device like the CP is a necessary small sub-circuit in many power module units. It is emerging research area within the on-chip circuits [1]. The charge pump used in non-volatile, like EEPROM and Flash memory, requires low input voltage and current in the millivolt range. Generally, two parameters play a very crucial role in designing charge pump, that is efficiency and low power [2].

The Dickson charge pump is a simplified circuit as it can make use of a single-stage charge pump using single MOS transistor and capacitors. While other charge pump circuits are more involved in design than Dickon charge pumps. Its power consumption is less as compared to other architectures [3].

Figure 1.

Basic module of boost circuit.

Figure 2.

MOS circuit designed using MOS capacitor with include LC combination.

However, the problem of threshold voltage drops and efficiency is seen in Dickson CP [4]. Researchers generally do not like to use four-phase clocks because of increased circuit complexity that is an unnecessary burden on chip area.

This work is carried out of my previously published paper, which used several associated techniques in the Dickson charge pump [22, 23, 24].

Two-phase clock is preferred due to reduced load on the circuit layout chip area. The PMOS based CP is suffer from mobility and current drive capability issues, so generally, NMOS based architecture is commonly used [5]. The design consideration follows as per designer need, also mentioned in Table 1.

Table 1

Design consideration follows as per designer need, in Table 1

Designer need to understand	Design of better charge pump
• System supply voltage • Transistor specification • Minimum layout size area • Better reliability and performance • Low ripple voltage	• Better Power efficiency • Low patristics capacitances. • Charge pump should have delivered more current at given regulation level • Using integrated inductor

Designer need to understand

Design of better charge pump

•

System supply voltage

•

Transistor specification

•

Minimum layout size area

•

Better reliability and performance

•

Low ripple voltage

•

Better Power efficiency

•

Low patristics capacitances.

•

Charge pump should have delivered more current at given regulation level

•

Using integrated inductor

The charge pump is an essential block in most energy harvesting systems, especially the ones targeting biomedical implant applications. Instead of using many small energy transfers a switch designed by MOS circuit can be used to reduce the circuit complexity of the charge pump [6]. An inductor can store and release energy quickly but never charge zero due to basic characteristic of the inductor. Therefore, the inductor is a better choice for the design to reduce the ripple in output voltage and also can improve efficiency [7].

Figure 3.

Ripple cancellation by LC circuit.

Figure 4.

Inductor maximum current is proportional to boost voltage.

In this proposed architecture, DCP circuit uses MOS capacitor in a novel architecture that reduces ripple by cancellation using LC combination. boosting clock using NAND gate in a DCP also helps to faster clock cycle with minimized dynamic power consumption [8].

The methodology of my proposed architecture is described in Section 2 to Section 7, Section 8, 9 is described simulation result of proposed charge pump and final conclusion in Section 10.

2. Proposed circuit using MOS capacitor

The suggested architecture is a new design using MOS capacitors, and two integrated inductors can be designed on-chip through a metal wire, as shown in Fig. 2.

The current value can be taken up to 100 nH due to limitation of integrated inductor which made by metal wire, therefore, cannot keep its value very high but it is good solution for on-chip design, and to avoid external inductor. Inductor helps to reduce ripple by cancellation. The charge loss during energy conversion through parasitic effect can reduce to a great extent by using the mos capacitor. It uses as a pumping capacitor with high voltage clock to overcome the problem of threshold drop at every stage [9]. It can achieve 3.5 V the ripple-free using integrated inductor due to the nature of inductor. which can cancel the ripple voltage in the output as shown in Fig. 3, also details described working of an inductor in Section 3.

From Fig. 2, the five-stage modified (Dickson charge pump) LC tank converter can be well-matched power in inductive-capacitive structural design to fabricate in a standard low-voltage CMOS process. A model LC tank DC converter is formed using a switch, an inductor, and a diode-attached MOS, as shown in Fig. 5. The charge pumps up to boost approximately five times that can generate output voltage 3.5 V from input voltage of 1.0 V. The energy of inductor used in the charge pump is inductor energy given by

Inductor energy

$\displaystyle\text{Inductor energy }E=\frac{1}{2}Li^{2}$ (1)

$V_{DS}$ of MOS resistance can be determined by

$\displaystyle\bm{I}_{\max}=\bm{I}_{{L}}-\bm{I}_{{C}}$ (2) $\displaystyle Req=\frac{L}{\mu Cox\times{(V_{\text{DD}}-V_{\text{THN}})}^{2}% \times W}$ (3) $\displaystyle i_{L}=C_{2}\times\frac{\partial vc_{2}}{\partial t}=\frac{(% \Delta V-V_{\gamma})}{\omega\times L}\sin(\omega\cdot t)$ (4)

using the above equation from Massimiliano Zucchelli [10]. Current spike and noise can be reduced in the output of the charge pump circuit through the LC circuit. Generally, Parallel LC circuit provides current enhancement and it is used as a load impedance in the RF amplifier also to obtain more gain in the resonant frequency [9].

Figure 5.

MOS equivalent series resistance [6].

Figure 6.

Transition activity of current and voltage for the L-C circuit.

Figure 7.

LC circuit Energy during the working.

Normalized peak impedance is $\bm{Q}\approx\frac{{\bm{Z}}_{\text{peak}}}{\sqrt{{\bm{L}}/{\bm{C}}}}$ .

3. Significance of the LC tank circuit

If boosting input voltage increases, then peak current is also increasing due to property of inductor as shown in Fig. 4. Receiving better enhance current through LC resonant circuits [10]. From Fig. 5a, when the inductor current reaches an optimum level then capacitor (show Purple) has charged to the input voltage then no difference after this effect of the current will stop, the inductor current will come back to zero. (Shown in green) Because of the inductor in the circuit, there is no sudden change in the circuit because, at that time, the inductor acts as a voltage source [12, 13]. As long as the value of the inductor current is zero, it is flowing in the same direction. As shown in Fig. 6b, Thus, it takes some time to decay until the current is zero, in this process energy stored in the inductor, is transferred to the capacitor, as shown in Fig. 6c. Hence the capacitor charge is twice of the supply voltage.

At low voltages, it is difficult to achieve greater efficiency on integrated circuits, but can be attained with the help of LC circuits [14]. In this proposed architecture, two LC circuits are used, at the first and the last stage, so the ripple voltage is reduced progressively from the first stage to the final stage. The LC arrangement maintains the level of current in the circuit. The desired frequency can be adjusted through the values of L and C.

$\displaystyle\bm{f}=\frac{1}{\sqrt{\bm{LC}}}$ (5)

The current level (up to 100 nA) and frequency (up to 150 Mhz) can be maintained by L and C values, in which the circuit can work well. However, with no separate inductors required in this circuit, it can be designed by spiral metal wire on-chip. It is a better way to increase efficiency and reduce the ripple voltage at the output [15].

Figure 8.

Shape of coil based integrated planner inductor.

Figure 9.

Symbol and connection of two-terminal NMOS capacitor.

Figure 10.

Applied gate voltage vs MOS capacitance (in pF).

As shown in Fig. 4, The L and C energy maximum up to 0.5 CV ${}^{2}$ , thus total energy is constant- no power dissipation in simple LC circuit but it moves from the capacitor to the inductor and back to capacitor every half period of oscillation as shown in Fig. 7.

Power absorbed by Series L-R Circuit,

$\displaystyle P(t)=I(t)\times V$ (6) $\displaystyle V(t)=I\times R+L\frac{{\rm d}i}{{\rm d}t}(\mu W)\text{ at }t=0$ (7) $\displaystyle P=i^{2}R+Li\frac{{\rm d}i}{{\rm d}t}(\mu W)$ (8)

where the ${i}^{2}R$ term represents the during switching, and power consumes through the resistor and $Li\frac{{\rm d}i}{{\rm d}t}(\mu\bm{W})$ Power consumed through an inductor. During high to low transition, energy is fully delivered from the inductor to capacitor [16]. Change in voltage in LC circuits is

$\displaystyle\Delta V_{C}+\Delta V_{L}=0$ (9) $\displaystyle\frac{Q}{C}-L\frac{{\rm d}I}{{\rm d}t}=0\left(I=-\frac{{\rm d}Q}{% {\rm d}t}\right)$ (10) $\displaystyle\frac{Q}{C}-\frac{{\rm d}}{{\rm d}t}\left(-\frac{{\rm d}Q}{{\rm d% }t}\right)=0$ (11)

The relation between charge $Q$ and current $I$ is depending on the rate of charging current during discharging of capacitors.

$\displaystyle\frac{Q}{C}-L\frac{{\rm d}^{2}Q}{{{\rm d}t}^{2}}=0\to Q=LC\frac{{% \rm d}^{2}Q}{{{\rm d}t}^{2}}$ (12)

Figure 11.

(a) Two possible operating points of a self-biased circuit. (b) A start-up circuit.

Figure 12.

Capacitive Divider feedback Control circuit.

4. Spiral shape on-chip inductor

The quality factor of a spiral planar inductor is up to a limit. It can be designed in layout easily on an integrated chip with the help of copper metal wire, details description as shows Fig. 8. But it can be designed to work in only a fixed frequency range, so inductor value is within 100-200 Nano-Henry [17].

Charge variable describe by second order differential equation.

$\displaystyle f=\frac{\omega}{2\pi}=\frac{2\pi}{T}=\frac{1}{2\pi\sqrt{LC}}$ (13)

it is a better option for low power applications. However, it is challenging to design external inductor on-chip. So integrated inductor is better option for on-chip designing. The diameter of spiral inductor Din(inner) and Dout (outer), coil width is $w$ , $S$ is separation between the coil.

5. MOS capacitor

The benefit of the presented architecture is the reduction of the effects of the parasitic by using MOS capacitors in each pump unit. The MOS capacitor is built using a terminal connected to the connected source and drain connections. As such, the MOS acts as a MIM capacitor with two terminals, and the MOS structure is shown in Fig. 9. A better alternative to reduce circuit area is by using MOS capacitors in place of MIM capacitors [18]. An industrial designer generally prefers MOS capacitors because it is easy-to-fabricate on-chip design without requiring an additional manufacturing step and also of low-cost advantage. The MOS capacitor relies heavily on voltage of the source, as are the C/V properties of the MOS capacitance, as shown in Fig. 9. W, L, and Tox values are decided according to technology specifications. They calculate the MOS capacitance by Eq. (14), describes the value parameter according to the technology.

$\displaystyle{\rm C}_{\rm OX}={{\rm C}^{\prime}}_{\rm OX}\times{\rm W}\times L$ (14) $\displaystyle{\rm C}^{\prime}_{\rm OX}=\frac{\varepsilon_{\rm OX}}{T_{\rm OX}}% \frac{\text{farad}}{\text{meter}^{2}}$ (15) $\displaystyle{\rm C}^{\prime}_{\rm OX}=\frac{\varepsilon_{\rm OX}}{T_{\rm OX}}% =\frac{3.45\times 10^{-11}}{8\times 10^{-9}}=4.32\times 10^{-3}\frac{f}{\mu m^% {2}}$ (16)

From Fig. 10, The capacitance of MOS capacitor depends on the applied gate voltage, which applied on gate terminal and body is grounded is made by tied to source and drain terminal, MOS capacitor increases in forward-biasing and decreases with reverse bias gate voltage. MOS capacitor generally called junction capacitor. Its capacitance is very low, whose value is in the range of femto-fared, whose value can be set by the W/L ratio, according to the technology node, with the help of equation as 14 and 15. The minimum capacitor reaches near the threshold voltage and higher capacitance reaches at higher voltage. So this is very useful for on-chip MOS capacitor based charge pump design.

Table 2

Simulation design parameter using cadence 180 nm technology Table 2

Device and component description	Parameter value
Tool used	Cadence Virtuoso IC616
Technology used	180 nm
MOS capacitor used as Pumping capacitor	$L=$ 20 $\mu$ m, $W=$ 20 $\mu$ m $=$ 1.09 pf
LC combination (used in 1 ${}^{\text{st}}$ and last stage)	$L=$ 100 Nano henry, $C_{1}=$ 1 pf to $C_{2}=$ 2 pf
Supply voltage	1.0 V
Output voltage	3.5 V
Frequency	100–150 MHz

6. Threshold voltage self-biasing

Figure 13.

output voltage with a frequency.

Self-biasing using current source. In self-biasing techniques, the current source is dependent on supply voltage and temperature and the circuit current will be affected during changes in Vdd and Vss. Biasing techniques will reduce the effect of power supply variation.

From Fig. 11, in the biasing circuit the transistor M1 and M2 have equal current flow, and the voltage applied through M3 and M4, is $I\times R=$ Vgs of M1, and it will ignore Rout and Body effect [19].

$\displaystyle IR=V_{\rm GS1}=V_{\text{THN}}+\sqrt{\frac{2I}{{\beta}_{1}}}$ (17)

If ${\beta}_{1}$ is greater, then $I$

$\displaystyle I\approx\frac{V_{\text{THN}}}{R}$ (18)

Figure 14.

Total power of system architecture.

Figure 15.

Total current of system architecture.

Then current is

$\displaystyle I=\frac{V_{\rm GS1}}{R}$ (19)

where the actual value of $V_{\rm GS1}$ is in the range 1.0 to 1.2 V from the above described equations. Thus it can be said that the current does not depend on the supply voltage.

Figure 16.

Power dissipation of charge pump circuit.

Figure 17.

Final output voltage of charge pump.

Figure 18.

Temperature behavior of 5 stage charge pump.

Figure 19.

Simulation result of monto carlo on temperature and current.

7. Feedback capacitive-divider control circuit

The fastest capacitive feedback divider control is better than resistor divider, as shown in Fig. 5, Shifting of voltage is necessary for the desired output voltage and is set through reference voltage using a voltage divider feedback circuit. It is compared by giving two input voltages $+V_{\text{REF}}$ (reference voltage) and $-V_{\text{DIV}}$ (divider input voltage) that is present in the control circuit. A proper technique for regulation involves sampling the pump output voltage and reference voltage to compare the sample changes in voltage with the known reference voltage in the amplifier [20]. To maintain the output level through $C_{1}$ and $C_{2}$ , their values change with parasitic capacitance. The capacitive loading on the pump maybe insignificant to $C_{\text{Load}}$ . The feedback control does not take power after the output of the pump is controlled. It produces no current from the output of the charge pump [21]. They maintain the current level and power loss through the divider circuit.

$\displaystyle V_{\text{Div}}{\times C}_{2}+C_{1}\times(V_{\text{Div}}-V_{\text% {output}})=0\times(C_{1}+C_{2})$ (20) $\displaystyle{V}_{\text{output}}\times C_{1}=V_{\text{Div}}\times(C_{1}+C_{2})$ (21) $\displaystyle V_{\text{Div}}=V_{\text{output}}\times\frac{C_{1}}{C_{1}+C_{2}}$ (22)

Div $=$ 0, where is $+V_{\text{REF}}$ is regulated the output. After starting the regulation, the initialisation device is closed or switched off. Div ignored leakage current The conservation of the charge is observed on the node at all times, Assuming each variation component is independent of the applied negative voltage $V_{\text{REF}}$ .

$\displaystyle{\rm V}_{\rm REF}={\rm V}_{\text{output }}$ (23) $\displaystyle{\rm V}_{\text{output}}={\rm V}_{\rm REF}\times\left(1+\frac{{\rm C% }_{2}}{{\rm C}_{1}}\right)$ (24)

8. Simulation result of a proposed circuit (transient analysis)

From Fig. 13, The output voltage of the charge pump circuit in 5 stage using MOS capacitor-based LC circuit, reaches up to 3.5 volts with ripple-free under the 5 $\mu$ s fast transient response simulation time. It is better to use MOS capacitor at frequency range 122 MHz to 140 MHz MOS capacitor can work in a limited range of frequency, so it is desirable.

The total achieved power of system architecture is 5 mW in the transient analysis, as shown in Fig. 14. The 5 mW is maximum power during the transition of the clock signal to achieve till target voltage, with the average output power is 2.5 mW.

From Fig. 15, The total output current of system architecture is 125 $\mu$ A, where the average current is 25 $\mu$ A and constant current maintains up to regulation level using the self-biasing circuit. From Fig. 16, it is shown that the power consumption of the charge pump

block varies from 100 $\mu$ W to 700 $\mu$ W, with Vout from 1 V to 3.5 V. Using the MOS capacitor, this is a near ideal result. From Fig. 17 it is shown that the output voltage goes up to 3.5 V with two non-overlapping clock signals. From Fig. 18, The temperature effect in variation of the output voltage is seen as 6 millivolts which is very low whereas the temperature related variation in the clock signal is 30 microvolts.

The result analysis from Monto carlo simulation, after designing and simulating the circuit, the result is as predicted by the theoretical analysis. As from shown in Fig. 19, the Monte Carlo simulation, the designer changes the value, such as the temperature and voltages, separately to

see how the circuit will react with the measurement of the actual voltage values. This simulation result basis on the temperature at 270C to, which is variation 5.38 mV at the output which is showing Fig. 19, also shows in Fig. 18. Which is acceptable for proposed architecture.

9. Conclusion

MOS capacitor-based proposed modified Dickson charge pump has been designed from an economic point of view of making easy-to-fabricate, that can also reduce the parasitic effect on the pumping capacitor. We found that this can reduce up to 90% ripple voltage by using LC combination in the first stage and last stage. To maintain the current level in the circuit up to the last stage by using an integrated inductor (spiral planner square shape) with values $L=$ 100 Nano henry. The Proposed 5 stage modified Dickson charge pump circuit is simulated in Cadence-Virtuoso environment by using 180 nm technology. It achieves output voltage up to 3.5 V from 1.0 V input. Use of control circuit is done to provide regulated output through faster capacitive divider feedback control. It can also reduce the parasitic effect through C1 and C2 values. Self-Biasing circuit provides the constant current to input section as no variation is generated during its operation; another reason for this is that the current is independent of supply voltage. This circuit can be used in non-volatile memory, and white LED Driver or Portable Device-Based Applications.

Footnotes

Acknowledgments

I am very grateful to the RGNFS Fellowship by UGC for promoting and providing financial support to Ph.D., research in the field of VLSI design.

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