A power-aware algorithm for the design of reconfigurable hardware during high level placement

The popularity of reconfigurable logic devices and portable hardwaredemands ever increasing power saving schemes for low power designs. Thispaper looks at the CAD design process of reconfigurable devices andpresents a novel method to gain power savings during the placement stage ofthe CAD flow. The proposed system modeled the number of switches used inthe circuit and employed simulated annealing algorithm to reduce theoverall routing power. The system was tested against 8 large benchmarkcircuits. It was able to achieve a routing power saving of up to 18%compared with cases without modeling the switches.