Journal of High Speed Networks

This document outlines an architecture and implementation plan for the National Science Foundation's Interagency Interim National Research and Education Network (NREN) component of the HPCC Program. The Interagency Interim NREN is intended as a near term research and development program to extend the capabilities and breadth of connectivity of today's research and education (R&E) networks. This network will provide not only the opportunity for agency backbones and mid-level networks to connect to NSF-funded networks, but also act as a limited testbed for new technologies in the migration to a gigabit NREN. In order to ensure a smooth transition to a national gigabit network infrastructure which can support the combined requirements of federal agencies, the U.S. research and educational institutions, and industrial collaborations with U.S. R&E institutions, the National Science Foundation has collaborated with other federal agencies in establishing this framework for the Interagency Interim NREN.

We have proposed a new architecture called Axon that meets the challenges of delivering high network bandwidth directly to applications. Its novel aspects include: an integrated design of host and network interface hardware, operating systems, and communication protocols; the proper division of hardware and software function; reorganisation of end-to-end protocols to take advantage of the increased functionality of the emerging high speed internetworks; and a pipelined interface between the network and host memory with no packet buffering.

The pipelined network interface performs critical per packet processing in hardware as packets flow through the pipeline, without imposing any store-and-forward buffering of packets. This requires the design of error and flow control mechanisms to be simple enough for implementation in the network interface hardware, while providing the functionality required by applications.

This paper describes the design of the host-network interface, and, in particular, the hardware design of the critical per packet processing with emphasis on error and flow control. An extensive simulation model of the network interface hardware has been used to determine the feasibility and performance of hardware implementation of these functions.

A novel multigigabit, multichannel lightwave network is described which uses subcarrier multiplexing to place multiple information channels and a baseband control channel on a single optical carrier. The control channel uses an FDDI-like token-passing access protocol and a 100 Mb/s control channel to provide efficient access to many Gb/s of information. The subcarrier multiplexed network (SCM-NET) can simultaneously transport many forms of information including variable-length data-grams, ATM-cells, and connection-oriented video traffic. By channelizing the total throughput, the reduction in utilization efficiency caused by propagation delay between nodes is significantly improved relative to conventional single-channel gigabit networks.

The leaky bucket algorithm has been proposed as an important element in the rate-based management of bandwidth in high-performance, integrated packet communication networks. In this paper, the leaky bucket algorithm is analyzed for ON-OFF data sources, which may be characterized by their average data rate, peak data rate, and average number of bits generated during an ON period. A fictitious queue is used to model the behavior of the leaky bucket algorithm, and a two-state Markov-modulated rate process is used to model the ON-OFF data source. The analysis applies to buffered and unbuffered leaky buckets with rejecting or marking of violating data. Simple, closed-form expressions are derived that relate the leaky bucket parameters (bucket size and rate) and the ON-OFF source characteristics to the loss and mark probabilities and the leaky bucket queueing delay. The required bucket size is shown to increase linearly with the average number of bits generated during an ON period, and increase logarithmically with the decrease in loss or mark probability. For a buffered leaky bucket, we also show that the bucket size increases logarithmically with the decrease in the average delay in the leaky bucket queue.