A study on passivation improvement in n -passivated emitter rear totally diffused solar cell using rapid thermal annealing

Abstract

An investigation on enhanced surface passivation in the existing industrial process line of large area n-type silicon (Si) Passivated Emitter Rear Totally diffused (n- PERT) solar cell has been performed. The Rapid Thermal Process (RTP) optimization for 20 min is conducted in the temperature range of 500–900°C and device evaluation is carried out with respect to regularly processed n-PERT solar cell. The impact of pre-metallization annealing is studied with the support of cell parameters like shunt resistance, reverse saturation current density determined from current-voltage measurements. The enhanced surface passivation via hydrogenation from silicon nitride (SiN_x) layer during annealing is established with the help of external quantum efficiency, spectral response measurements and Fourier transform infrared spectroscopy analysis. The addition of optimized annealing resulted in improvement by 550% (from 38 to 247 µs), 7.73% (from 630.7 to 678.8 mV) and 84.77% (from 223.3 to 34 cm/s) in effective minority carrier lifetime, implied open circuit voltage and surface recombination velocity respectively. Finally, RTP technique for optimized process line has been successfully incorporated in industrial high-volume batch of 140898 CZ n-type Si wafers, which predicts conceptual validation of the study in mass scale production line with an increment in average efficiency of the device by 0.35%.

Keywords

RTP annealing external quantum efficiency effective carrier lifetime surface recombination velocity implied open circuit voltage

1. Introduction

The generation capacity of renewable energy across the world is increased by 176 Gigawatt (GW) in 2019. The wind, solar energy based renewable sources have contributed 90% of the capacity of total renewable energy added in this year and in these technologies solar energy alone added 98 GW. Thus, solar energy-based technologies have outperformed all rest other renewable technologies and has seen tremendous expansion globally in installation from few Megawatt (MW) to close to 100 GW.¹ Amongst these technologies, the photovoltaic (PV) industry continued to face relentless competition due to pressure of lower prices and higher solar module power output cost

In recent years, to address the scarcity of energy, the PV industry has grown rapidly with various associated technologies in this direction. Out of all technologies, the conventional p-type crystalline silicon (c-Si) cells lead the whole PV market.² This type of standard c-Si solar cell has n-type and p-type semiconducting layer as emitter and base respectively along with full aluminium back surface field. The texturization and doping followed by silicon nitride (SiN_x) passivation layer on the front and then screen-printed silver paste metallization can produce c-Si solar cell efficiency up to ∼ 20%.^3,4 But these p-type c-Si solar cells have high temperature coefficient, serious light-induced degradation^5,6 and light and elevated temperature induced degradation, which shrink the performance of Si solar cell and drop in electricity power generation during its field application in solar panels. If c-Si solar cell device architecture is based on n-type wafer then the fabricated device has no detrimental effect of light-induced degradation and elevated temperature induced degradation. These advantageous features in n-type c-Si solar cells are ascribed to the absence of boron doping in base layer of solar cell. So far, commonly reported n-type Si wafer-based technologies are heterojunction with intrinsic thin layer,⁷ interdigitated back contact,^8,9 tunnel oxide passivated contact¹⁰ and passivated emitter rear totally diffused (PERT) in laboratory scale.¹¹ To address challenges in efficiency enhancement of p-type c-Si solar cells, the continuous developments such as surface passivation,^12,13 laser opening¹⁴ and aluminium screen-printed local back surface field¹⁵ are needed. Based on the surface passivation idea, a variety of solar cell architecture like passivated emitter rear locally diffused (PERL), passivated emitter rear contact (PERC) and PERT devices are recommended for the fabrication of high efficiency solar cells.¹⁶ The PERT technology is at large most suitable technology for mass production at present amongst all and this mono or polycrystalline Si wafer based solar cell technologies offer relatively simple involved processes and moderate cost In addition to it, the bifacial structure of PERT can take benefit of the diffuse reflection light on the rear, which further escalates the power generation output. Amongst all, n-type c-Si wafer-based technology i.e., n-PERT provides advantages such as superior tolerance to general impurities (e.g. iron),^17,18 high bulk lifetime and near zero light-induced degradation. So, as a result, n-type crystalline-Si based PERT structure Si solar cell provides advantage of high working efficiency of solar cell which involves process optimization in a cost-effective manner.

Currently surface passivation of defects is critical in Si wafer-based PERT solar cell technologies to evaluate device performance. In these technologies, in-situ grown boron silicate glass during boron diffusion on Si surfaces forms unsatisfied silicon bonds. These unsatisfied bonds show energy states lies within the silicon material band gap and so generate several recombination centers. These recombination centers or defect levels hinder the charge carrier movement and so reduces minority carrier lifetime significantly.¹⁹ Though thermal oxidation step drastically reduces these trap centers compared to the bare Si surface but still the processing steps for device formation introduce defects in such manner that these bonds still remain unsatisfied significantly after oxidation. Further rise in recombination centers in Si after oxidation can be attributed to subsequent processing step such as firing steps required for the formation of the screen-printed front and back contacts. Many research groups have reported efficiency enhancement through surface passivation in Si solar cell due to the thermal annealing incorporation at different processing stages such as before SiN_x layer, after SiN_x layer or during metallization with annealing temperature range (500–1000°C) which depends on type of doping processes (ion implantation or diffusion) and type of Si wafer (n or p-type) used in PERT device architecture.^20–22 These studies show that thermal annealing after boron and phosphorous doping in front and rear surface of bifacial solar cell at higher temperature range (950–1050°C) has resulted into appreciable enhancement in absolute efficiency of ∼0.5%. The high temperature (>1000°C) annealing is prerequisite to fully activate ion implanted boron atoms at front surface for the increase in surface passivation. Recently, a research group reported pre-firing annealing (550–750°C) process prior to metallization in device fabrication line and found it to be promising for efficiency enhancement of the device. This device comprised phosphorous diffused doping on both sides of p-type multicrystalline Si (mc-Si) wafer.²³ The reported work signifies the importance of pre-firing annealing (temperature range 550–750°C) in mc-Si wafer based bifacial p-PERT- solar cell for short duration (3 s to 6 min) and observed efficiency enhancement via hydrogenated SiN_x layer into Si which is leading to the minimization of the dangling bonds in emitter and bulk surface. Thus, minimum annealing temperature (>500°C) is required to activate unsatisfied bonds in Si surface for bonds saturation. Herein, an investigation on optimization of this pre-firing named as pre-metallization annealing is performed for enhancing surface passivation in the n-type monocrystalline Si wafer-based PERT i.e. n-PERT solar cell production line. This device comprises boron and phosphorous diffusion in front and rear surface and RTP is carried out in the temperature range of 500–900°C for 20 min. Our previous study already depicts efficiency improvement due to pre-metallization thermal annealing in the temperature range of 500–900°C for 20 min in these n-PERT solar cells via I-V curve measurements. But it was limited to variation in solar cell output parameters such as open circuit voltage, short circuit current and fill factor of the devices with respect to annealing temperature only.²⁴ Now, we have extended this work and additionally supported this study with Fourier transform infrared spectroscopy, scanning electron microscope, external quantum efficiency, reflectance, electroluminescence and minority carrier lifetime measurements of fabricated devices, for optimization of device annealing temperature. Moreover, after optimizing this process line for a device, it is applied on a mass scale production line of total 140,898 n-type monocrystalline Si wafers, which confirm yield and reliability of this technology in the existing production line. All the related device parameters are analyzed in view of that of variation in RTP annealing temperature. The fabricated n-PERT solar cell device surface morphologies were analysed by Scanning Electron Microscope (SEM) (Make: Zeiss - EVO-18). Class AAA tester system for I-V measurement by cetisPV was employed for electrical evaluation of all n-PERT devices under AM 1.5G spectrum with solar irradiance of 1000 W/m² at device temperature of 25 °C. The minority carrier lifetime analysis was conducted using Sinton WCT-120 instrument in generalized analysis mode with minority carrier density injection of 10¹⁵ cm⁻³. Benthem PVE300 was used for External Quantum Efficiency measurements in the wavelength region of 300–1200 nm. In order to confirm hydrogenation effect in silicon-hydrogen bonding, Fourier transform infrared measurements was conducted using Perkin Elmer with ATR technique in the wave number range of 1000–3500 cm⁻¹. The Electroluminescence testing of fabricated n-PERT solar cell was performed using halm EL tester having short wavelength infrared high resolution CMOS camera.

2. Experimental section

The n-type monocrystalline pseudosqaure CZ Si (100) wafers of area 157.35 × 157.35 mm² with a specific resistivity of 2.1 Ohm-cm and thickness of 170 µm were employed in the fabrication of n-PERT solar cell. Initially, we removed the saw damage and conducted wafer cleaning process. Then, the micro texturing process was performed to form micro-pyramidal structure on wafer surface by wet chemical etching in alkaline solution at 80°C for 25 min. This was followed phosphorous diffusion using phosphorous oxychloride (POCl₃) as dopant source for the formation of rear emitter of n-type. This diffusion process was conducted till rear emitter achieves its sheet resistance to 110 Ω/sq. which was measured by in house set up for four-point probe method. After rear emitter formation, antireflection-coating (ARC) via SiNx deposition was carried out by plasma-enhanced chemical vapour deposition (PECVD) in Centrotherm cPLASMA tube furnace at temperature of 430°C. Post rear ARC with n-type diffused wafer is followed by front surface wet texturization using industrial type alkaline solution processed line comprising alkaline solution with industrial chemical additives to perform optimum etching of Si surface with suitable ambient conditions. This front textured Si wafer is subjected in Centrotherm diffusion furnace for boron diffusion via Boron tribromide (BBr₃) as a source dopant. The diffusion is performed to achieve front emitter of the cell with a sheet resistance of approximately 80 Ω/sq. This Boron diffusion of Si wafer confirms design of front emitter in the device which was followed with edge isolation using HF/HNO₃/H₂O chemicals. So formed front emitter is then deposited with SiN_x layer using PECVD tools at a deposition temperature of 430°C. All these processed Si wafers were also incorporated with the optimum use of phosphosilicate and borosilate glass which results into electron-selective (thermal-SiO_x/C-Si(n⁺)) and hole selective (thermal-SiO_x/C-Si(p⁺)) passivated contacts onto both sides of wafer with passivated (SiN_x) layer on front and rear emitter sides.

Finally, prior to metallization at the end of device fabrication process line, RTP annealing with N₂ ambient in the temperature range of 500 to 900°C was performed with an augmentation of 100°C for around 20 min in industrial tube furnace. The additional annealing effects due to RTP were analyzed at each temperature and optimized for enhancing solar cell efficiency. All these processed Si wafers with different RTP treatments were subjected to same screen-printed metallization on both side of the devices for electrical contacts (front and back) and then followed with co-firing at a peak temperature of 835°C using an industrial infrared firing furnace (Centrotherm). The same metallization conditions for each device were implemented in as fabricated n-PERT solar cells (without and with annealing at different RTP temperatures). Since, optimization of RTP annealing was performed just before the metallization therefore herein it is termed as pre-metallization annealing also. The process flow chart of n-PERT device fabrication for without and with annealing are shown in Figure 1((a) and (b)). A typical adopted device architecture of n-type Si wafer-based PERT solar cell technology is shown in Figure 2.

Figure 1.

Process flow chart of n- PERT solar cell (a) without and (b) with RTP annealing.

Figure 2.

Device architecture of n-PERT solar cell.

3. Results and discussion

3.1. Surface analysis

The surface morphology of as fabricated n-PERT cell is being analyzed by Scanning Electron

Microscope. The front surface of the device is shown in Figure 3(a) and shows formation of pyramids type structure after alkaline texturization of the surface. These pyramid's dimension is found to be lying in the range of 2–3 µm and is confirmed the same from Figure 3(b) in tilted view. The screen-printed metallic finger on top of textured surface is shown in Figure 3(c), which confirms standard alignment of metallic fingers along with binding on textured Si surface. The metallic particles in these screen-printed fingers with higher magnification are also shown in Figure 3(d) and confirm that after fast firing it has formed better inter-particle bonding.

Figure 3.

SEM images of (a) textured surface (b) textured surface-tilted view (c) metallic finger on textured surface (d) metallic particles of fingers in a typical n-PERT solar cell.

3.2. Reflectance study

The reflectance measurement of front surface of fabricated n-PERT solar cell for without annealing and with optimized annealing of 700°C in the wavelength region 300–1200 nm are shown in Figure 4. The observed reflectance shows no appreciable change in reflectance due to annealing and both reflectance spectrum are matching with typical antireflection (SiNx) coated and textured silicon surface.

Figure 4.

Reflectance spectra of without and with annealed n-PERT solar cell.

3.3. Electrical characterization

3.3.1 External quantum efficiency analysis

Figure 5 shows the external quantum efficiency response of the n-PERT c-Si solar cell at different pre-metallization annealing temperatures with the wavelength region of 300–1200 nm. The reference (without annealing) sample has an average external quantum efficiency (EQE) of 77%, while cells treated with annealing temperature at 500, 600, 700, 800 and 900°C have average EQEs of 81.3%, 82.5%, 82.8%, 82.3% and 77.3% respectively, over the entire wavelength range 300–1200 nm. The solar cell treated with annealing temperature 700°C has the highest improvement in the short wavelength region (300–400 nm) while relatively lesser appreciation is observed in visible (400–700 nm) and near infrared (700–1200 nm) wavelength region for optimized pre-metallized annealing at 700°C with respect to untreated device. The overall major improvement in external quantum efficiency is observed in wavelength range of 320–580 nm for annealed devices. Furthermore, the cell treated with annealing temperature at 900°C shows the decrease in EQE compared with other annealed samples and reference (without annealing) sample, indicating that the photo response is decreased with the increase in the annealing temperature beyond 700°C. The average weighted EQE in UV (300–370 nm) and visible (400–700 nm) regions for n-PERT Si solar cell are shown in Figure 6. The highest weighted EQE % in UV region for annealed sample at optimized temperature of 700°C is 66.27% in comparison to that of 62.5% for untreated sample. The average weighted EQE increase in short wavelength region clearly indicates improvement in front surface passivation or decrease in front surface recombination in the device.²⁵ The least weighted EQE in UV region for sample annealed at 900°C confirms significant front surface degradation at higher annealing temperature with respect to controlled sample, which can be ascribed to effusion of hydrogen at higher annealing and therefore reduction in passivation of the dangling bonds in bulk of Si wafer occurs.

Figure 5.

EQE measurement of without and with annealed n-PERT solar cell.

Figure 6.

Weighted EQE in UV region for without and with annealed n-PERT solar cell.

Figure 7 shows the spectral response of the six different n-PERT Si solar cells in the wavelength region of 300–1300 nm. The average weighted spectral response value of without annealed device is 0.1702 A/W-nm while device treated at 500, 600, 700, 800 and 900°C are 0.1710, 0.1759, 0.1808, 0.1758 and 0.1222 A/W-nm respectively. The improved front surface passivation and so reduced recombination can be confirmed via increase in spectral response in short wavelength region.²⁶ The cell treated with annealing temperature at 700°C for 20 min clearly indicate highest spectral response value compared with the other annealed cells as well as reference (without annealed) cells. The measurement shows maximum increase in average weighted spectral response value for device annealed at 700°C which is an enhancement of 6.2% with respect to without treated device in the short wavelength region of 300–370 nm. This spectral response of the device in short wavelength region is degraded with increase of annealing temperature beyond 700°C and the decrease in response is found to be significantly to 28.2% with respect to untreated device at 900°C. This least spectral response in short wavelength region confirms front surface deterioration of n-PERT solar cell due to higher temperature annealing i.e. at >700°C.

Figure 7.

Spectral response measurement for without and with annealed n-PERT solar cell.

3.3.2 Current-Voltage (I-V) analysis

The shunt resistance is caused by defects on Si surface and in the bulk as well as from leakage currents or alternating current path across the edge of the cell. This parameter shows a parallel high-conducting path across the p-n junction which causes a reduction in both amount of current through the junction and voltage. The reduction in current and voltage decreases the efficiency of the cells by increasing the leakage current (measured by reverse saturation current (I_o)) that lowers the maximum output power (P_m), the open-circuit voltage (V_oc). The R_SH of a solar cell is determined using illuminated I-V characteristics of the cell extend from the fourth to the third quadrant while I_o can be evaluated by dark I-V measurement.²⁷ Thus, R_sh and I_o are crucial cell parameters to its performance during its field applications in the PV panel. The I-V equation for a solar cell under illumination in the presence of a shunt resistance is given by²⁸

I = I_{L} - I_{o} {\exp (q V + I R s) - 1} - \frac{V + I R_{S}}{R_{S h}}

(1)

where I_L, I_o, R_s are light generated current, reverse saturation current and series resistance, respectively.

The study of measured I-V curves were already reported in our previous communication, which is showing efficiency enhancement of n-PERT solar cell from 20.72% for without annealed to 21.03% for optimized annealed sample at 700°C. Accordingly, improvement in other output cell parameters such as, open-circuit voltage, short-circuit current and fill-factor (FF) variation with annealing temperature were observed. To extend this analysis further, herein shunt resistance (R_sh) and reverse saturation current density (J_o) variation extracted from I-V are presented in the Figure 8, which is showing variation of this parasitic resistance with rapid thermal annealing effect on the as-fabricated n-PERT solar cells. The Figure 8 clearly shows enhancement in R_sh due to annealing till optimized annealing at 700°C is achieved and then reduction is observed with increase in annealing temperature till 900°C. The exactly opposite behavior in reverse saturation current density with respect to shunt resistance is observed with increase in RTP temperature. The enhancement in shunt resistance from 2560 to 3931 Ω due to annealing till 700°C and reduction in reverse saturation current density from 771 fA/cm² for without annealed sample to 139 fA/cm² confirms reduction in crystalline defects, which helps in reducing recombination in the device. The reduction in recombination of carriers occurs due to increased hydrogen passivation via annealing, which assures better performance of the device during its field application.

Figure 8.

Shunt resistance and saturation current density variation for without and with annealed n-PERT solar cell.

Thus, optimized annealing at 700°C confirms achievement of minimum leakage current for this device. Hence, n-PERT solar cell annealed at 700°C confirms less crystalline defect along with least leakage current makes device to operate with higher working efficiency in field applications. The extracted data from I-V measurement are further summarized in Table 1.

Table 1.

Summary of extracted data from I-V measurement for without and with annealed n- PERT solar cell.

Cell	Efficiency	FF	I_sc	V_oc	R_s	R_sh	J_o
Cell	(%)	(%)	(A)	(V)	(mΩ)	(Ω)	(fA/cm²)
Without annealed	20.72	80.09	9.727	0.6549	2.193	2560	771
Annealed @ 500°C	20.79	80.11	9.728	0.6569	2.189	3102	494
Annealed @ 600°C	20.8	80.1	9.731	0.6573	2.198	3372	202
Annealed @ 700°C	21.05	80.21	9.765	0.6618	2.187	3931	139
Annealed @ 800°C	20.84	80.17	9.72	0.6584	2.147	2510	144
Annealed @ 900°C	19.5	79.94	9.433	0.6369	2.288	491	458

The above I-V table shows the electrical parameters of n-PERT Si solar cell treated with different annealing temperature. While comparing the electrical parameters of cells without and with optimized annealing temperature, unable to see any difference in series resistance. Since this annealing is performed before metallization process, so different annealing temperatures will not have any impact on finger or bus bar resistances. There is a possibility for changes in series resistance only due to lower surface concentration at higher annealing temperatures due to further drive-in and will lead to higher contact resistance during contact formation. Above table shows higher series resistance at annealing temperature of 900°C followed by the degradation of fill factor.

3.3.3 Electroluminescence image analysis

The qualities of screen-printed metallization on as fabricated without and with annealed n-PERT solar cells are observed by EL image testing, as shown in Figure 9. The annealing treatment is not at all affecting the front surface metallization of n-PERT solar cells as shown in below EL images.

Figure 9.

El images of without and with annealed n-PERT solar cells.

3.3.4 Photoconductivity analysis

To investigate the passivation effect, lifetime measurement was conducted using WCT-120 photo-conductance in generalized mode for analysing cell performance under minority carrier density of 10¹⁵ cm⁻³. The measured effective lifetime for as-fabricated and rapid annealed n-PERT solar cell for without and with RTP annealing are shown in Figure 10. Figure clearly depicts significant improvement in the effective minority carrier lifetime with the increase in RTP annealing temperature till 700°C. The variations in effective minority carrier lifetime for n-PERT solar cell due to RTP annealing at 500, 600, 700, 800 and 900°C are 56, 173, 247, 219 and 72 μs, respectively, while without annealed device show lifetime to be merely 38 μs. Thus, n-PERT solar cell shows significant enhancement in effective minority carrier lifetime from 38 μs to 247 μs for annealed sample at 700°C, which is almost 6.5 fold higher than controlled sample. A decrease in the improvement with respect to controlled device was observed after increase in pre-metallization annealing temperature beyond 700°C. A significant drop of ∼71% is observed for RTP annealed 900°C device with respect to the optimized one. This confirms that excessive RTP annealing at higher temperature is detrimental to minority carrier lifetime. Thus, lifetime evolution strongly depends upon the pre-metallization annealing temperature and on optimal RTP temperature in the device can help in improving minority carrier lifetime and confirm passivation of crystalline defects. The surface recombination velocity (SRV) is one of the most important determining parameters of surface passivation in a solar cell. Therefore, surface recombination velocity of the charge carriers is calculated for each annealed sample and compared it with controlled device. Herein, the as procured Si wafers features such as resistivity and thickness are used as 2.1 ohm-cm and 170 μm, respectively. The bulk lifetime ( $τ_{b u l k}$ ) of wafer is calculated and found to be 22.1 ms with minority carrier density injection of 10¹⁵ cm^−3.^29,30 The surface recombination velocity (SRV in cm/s) can be calculated from effective minority carrier lifetime ( $τ_{e f f}$ ) using standard equation,³¹

S R V = \frac{w}{2} (\frac{1}{τ_{e f f}} - \frac{1}{τ_{b u l k}})

(2)

where, w is wafer thickness (in μm) of Si wafer. Using equation (2), the calculated surface recombination velocities for without annealed n-PERT solar cell is found to be 223.3 cm/s. If devices are RTP annealed at 500, 600, 700, 800 and 900°C, the calculated respective SRV values for these devices are found to be 151.4, 48.75, 34, 38.43 and 117.67 cm/s, respectively. The variation in SRV with change in RTP annealing temperature are shown in Figure 10 and found that the minimum value up to 34 cm\s is achieved for optimized annealing in n-PERT Si solar cell at 700°C. The data clearly depicts a highest reduction of 84.7% in existing SRV value from 223.3 to 34 cm/s due to RTP annealing. This SRV value then again starts to rise to 38.43 and 117.67 cm/s with RTP annealing for 800 and 900°C respectively.

Figure 10.

The measured effective minority carrier lifetime ( $τ_{e f f}$ ) and calculated SRV for without and with annealed n-PERT solar cells.

The minority carrier injection in photoconductivity analysis also helps in evaluating the important device passivation parameter such as implied V_oc. The measured implied V_oc for all respective n-PERT devices are shown in Figure 11. This device performance parameter found to show variations according to the RTP annealing temperature profile and well-tuned and analogous to other surface passivation parameters such as $τ_{e f f}$ and SRV. The maximum achieved implied V_OC is 678.8 mV for optimized annealed n-PERT solar cell at 700°C temperature which is an enhancement of 7.6% with respect to without annealed device (implied V_oc = 630.7 mV).

Figure 11.

Implied V_OC for without and with annealed n-PERT solar cells.

3.3.5 Chemical characterization via Fourier transform infrared analysis

The oxide passivation step due to RTP annealing after phosphorus diffusion in the process line of device fabrication (Figure 1) causes further improvement in charge carrier lifetime values which leads to the reduction in surface recombination velocities and hence surface passivation via hydrogenated SiN_x layer occurs in the device.

Herein, atomic hydrogen diffuses from SiN_x layer through oxide layer and passivates dangling bonds. The mobility of bound hydrogen is critical as it is expected that the degree of passivation (as measured in minority carrier lifetime) depends on the amount of hydrogen released from the SiN_x film into the bulk of wafer.³² The release of hydrogen from SiN_x film is increased with RTP annealing temperature in the range of 500 to 700°C, which can be depicted via reduced hydrogen presence. This reduction of hydrogen leads to the removal of contaminants and structural defects from the bulk of silicon after cleaning and saw damage removal. The RTP annealing beyond 700°C results into out diffusion of hydrogen from Si-SiN_x interface and can be confirmed via increased silicon-hydrogen bonding at surface. This enhanced effusion of hydrogen from hydrogenated SiN_x results into reduction in surface passivation in the device.^33,34 Defect hydrogenation in Si is studied using attenuated total reflectance Fourier Transform Infrared spectroscopy. Figure 12 provides the Fourier Transform Infrared Transmission spectra for three hydrogenated SiN_x layers grown with RTP treated at 700 and 900°C temperature (sample B and C) and without annealed (sample A) n-PERT solar cell. In order to understand surface passivation through hydrogenation from SiN_x layer, most prominent feature is hydrogen bond associated with silicon and nitrogen in transmission spectrum. The transmission bands observed at around 2160 cm⁻¹ and 3340 cm⁻¹ are assigned to Si-H and N-H stretches.³⁵ The majority of H is bound to Si for without annealed n-PERT sample and measured transmission band is found to be with 0.94 change for sample A. If this device is RTP annealed at 700°C, a reduction in transmission band of Si-H is observed and change in transmission is found to be 0.78 as depicted in inset image of the Figure 12. This confirms reduction of hydrogen in silicon with increase of RTP annealing temperature till 700°C. This reduction in hydrogen is consumed in reducing defects of silicon and helping in enhancing bulk passivation of device. The outward diffusion of hydrogen from Si-SiN_x interface is confirmed from increased transmission band intensity (from 0.94 to 0.99) of Si-H bonding for n-PERT solar cell annealed at 900°C, which is shown as sample C in inset image of Figure 12. Thus, RTP annealing study in the temperature range of 500–900°C of n-PERT solar cell reveals that the associated mechanism involves hydrogen bond dissociation followed by molecular in and out diffusion depending on variation of RTP temperature which can lead to increment or decrement in surface passivation parameters measured by variations in charge carrier lifetime, implied V_oc, SRV values. All these passivation parameters are responding in similar manner to RTP heat treatment in n-PERT solar cell and maximum passivation is achieved for device annealed at 700°C.

Figure 12.

The Fourier transform infrared measurement for without and with annealed n-PERT solar cell.

4. Batch level device fabrication

The improved performance of large size n-PERT solar cell device is clearly showing enhancement of 0.33% in its absolute efficiency due to pre-metallization RTP annealing at 700°C. The optimized RTP annealing for improved device efficiency with n-PERT architecture (Figure 2) has been implemented in the batch process line. The device level study is further confirmed in mass production line with volume of 1,40,898 CZ Si wafers. Out of total CZ Si wafers, 61000 wafers were processed for device fabrication in absence of annealing and rest of wafers (79,898) were processed with RTP annealing at optimized temperature of 700°C in the n-PERT solar cell production line. The histogram represents efficiency distribution for without annealed and with annealed n-PERT Si solar cell in production line as depicted in Figure 13. The figure clearly shows percentage of cells at different efficiencies segregated within the band range of + 0.1% tolerance, i.e., all the n-PERT solar cells having efficiencies in the range of 21.00–21.10% will be notified as an average efficiency bin-of 21%. So, the histogram figure clearly shows that the optimized annealing temperature at 700°C treated cells depict highest efficiency compared to the without annealed device. The average efficiency of fabricated n-PERT devices at batch level for without and with optimized annealing are found to be 20.62 and 20.97%, respectively.

Figure 13.

Batch wise solar cell efficiency for without and with annealed n-PERT solar cell.

Thus, successful integration of RTP annealing in existing process line of a commercial large size CZ-Si wafers for n-PERT solar cell device fabrication is established in a large volume production line. An average efficiency of 20.97% was demonstrated over a large production batch with average absolute efficiency improvement of 0.35% due to optimized RTP annealing.

5. Conclusions

In this work, we demonstrate the potential of incorporating optimized thermal heat treatment via RTP annealing for enhancing n-PERT solar cell performance with the support of I-V, minority carrier lifetime, external quantum efficiency and spectral response measurements. Herein, pre-metallization annealing in n-PERT process line is performed in the temperatures range of 500- 900°C with an interval of 100°C. The measured I-V curves indicate enhancement in shunt resistance and reduction in reverse saturation current density with optimized RTP annealing (for 20 min) at 700°C. The SEM measurements confirm typical pyramid's height in the range of 2–3 µm after texturization of Si surface. The External Quantum Efficiency measurement shows highest UV response in the short wavelength region (300–400 nm) and shows improvement of ∼6.5% due to optimized RTP annealing at 700°C. The spectral response and external quantum efficiency measurements show better UV response in n-PERT solar cell and so validate front surface passivation in the device. The hydrogen diffusion and effusion in the solar cell due to RTP annealing is confirmed from Fourier Transform Infrared analysis via decrement and increment in transmission band intensity of silicon-hydrogen bonding. The solar cell surface passivation signature parameters such as effective minority carrier lifetime( $τ_{e f f}$ ), implied open circuit voltage (implied V_oc), SRV have shown significant improvement with RTP annealing till 700°C and thereafter these parameters are degrading with increase in RTP temperature till 900°C. The optimized RTP annealing confirms improvement in $τ_{e f f}$ , implied V_oc, R_sh, J_o and SRV from existing 38 µs, 630.7 mV, 2560 Ω, 771 fA/cm², 223.3 cm/s to 247 µs, 680 mV, 3931 Ω, 139 fA/cm², 34 cm/s, respectively, due to optimized RTP annealing which has resulted into defects passivation. Thus, hydrogenation in SiN_x layer with RTP annealing helps in the bulk passivation of Si wafer and optimized passivation is observed at annealing temperature of 700°C for 20 min of duration in n-PERT solar cell. Finally, this study demonstrates conceptual validation of efficiency improvement in n-PERT device via optimized RTP annealing in the running device production line and so successfully bridges the efficiency gap between the laboratory and the mass scale production with average efficiency enhancement in batch line of 79,898 n-type Si wafer solar cell by 0.35%. Hence this study depicts increase in solar cell efficiency in n-PERT technology via improved surface passivation due to optimized pre-metallization annealing in batch level processing. This improved technology establishes integration in production line and can ultimately help in achieving reduced price per watt of electrical energy in solar panel as it possesses both scalability and reliability feature.

Footnotes

Declaration of conflicting interests

The author(s) declared no potential conflicts of interest with respect to the research, authorship, and/or publication of this article.

Funding

The author(s) received no financial support for the research, authorship, and/or publication of this article.

ORCID iDs

Hrishikesh Dhasmana

Abhishek Verma

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