Architecture-driven voltage scaling for high-throughput turbo-decoders

The outstanding forward error correction provided by Turbo-Codes made them part of today's and emerging communications standards. Therefore, efficient Turbo-Decoder architectures are important building blocks in communications systems. In this paper we present a scalable, highly parallel architecture for UMTS compliant Turbo decoding and apply architecture-driven voltage scaling to reduce the energy consumption. We will show that this approach adds some additional, more energy-efficient solutions to the design space of low power Turbo decoding systems. It can save up to 34% of the decoding energy per datablock under realistic voltage assumptions. We present throughput, area, and energy results for various degrees of parallelization based on synthesis on a 0.18 μm ASIC-technology library, which is characterized for two different supply voltages: nominal 1.8 V and nominal 1.3 V.