CMOS implementation of a novel analog multiplier/divider to realize centroid strategy in defuzzifier block

Abstract

This paper, presents a CMOS design of a novel current-mode analog multiplier/divider which can be used in defuzzifier block for fuzzy logic controllers (FLC) and neuro-fuzzy systems to realize the centroid strategy. This analog multiplier/divider circuit operates based on the square-law characteristic of a MOS transistor operated in the saturation region. The proposed circuits are designed in 0.18μm CMOS technology with a power supply of 2 Volt. The maximum delay for the proposed circuit is 50.7 ns that restricts the inference speed of the total fuzzy logic controller to 20 MFLIPS in its turn. The maximum power consumption of this circuit is about 626μW and can be implemented in 84μm×36μm. The functionality of the proposed multiplier/divider in the defuzzifier block of a typical (3×3) FLC was evaluated and results indicate that the percentage of root mean squarer error (RMSE) of the output surface is 1.08% of the full scale output. To obtain the ideal output surface MATLAB software has been utilized.

Keywords

CMOS defuzzifier centroid strategy multiplier/divider current-mode four-quadrant

1 Introduction

Features like real time and nonlinear signal processing of fuzzy systems bring them up as an attractive approach for a vast range of applications such as automotive industry, robotics, home appliances and etc. [1 –4]. There are two general approaches for implementing fuzzy logic controllers: software [5] and hardware [6 –8]. The main deficiency of the software approach is its slow speed of operation which makes it suitable only for limited range of applications like mechanical or thermal processes which typically operate below KFLIPS rate (FLIPS stands for fuzzy logic inferences per second). The hardware implementation is categorized into three methods: analog [9 –14], digital [4 , 15–18] and mixed analog-digital [19 –22]. With respect to power consumption and “silicon area/inference speed” ratio, analog chips are more preferable than digital chips, because in digital chips for computing units like defuzzifier block, the designing of digital multiplier and divider circuits occupies a large chip area. Moreover, unlike digital chips in analog counterparts, additional circuits are not required to build the interface with sensors and actuators. However, the digital systems are much robust against noise and distortions that is considered as their main advantage. In mixed analog-digital chips, usually computing units (i.e. inference engine and defuzzifier block) are realized by analog circuits and digital circuits are used for programmability and reconfiguration purposes.

A conventional fuzzy logic controller consists of three basic units: fuzzifier (membership function generator (MFG)), fuzzy inference engine and defuzzifier block. In the analog technique, the improvement of features (e.g. speed, precision, power consumption and area) in each unit of the controller will cause aconsiderable enhancement on the performance of the total controlling system. Defuzzifier block is the last unit in fuzzy controllers and is used to obtain a crisp value by characterizing the output fuzzy set which is given by the inference process. In previous works, to realize this block Tsukano et al. proposed a current-mode analog circuit for fuzzy inference hardware system, in which the COG (center of gravity) defuzzifing strategy was carried out using BiCMOS translinear multipliers and dividers [23]. Tang and Lin proposed a defuzzifier circuit using resonant tunneling diodes [24]. For VLSI implementation, however, the need of a complicated fabrication process is a drawback of the mentioned works [25]. In [26], Tartagni introduced a low power current-mode analog circuit with MOS transistors operating in weak inversion to accomplish the centroid strategy. Nevertheless, the dynamic range of those circuits that operate in weak inversion is small. In addition, the speed of these circuits is low for general applications because of the inherent limitations of transistors in weak inversion [27].

In this paper, we present CMOS design of a new analog multiplier/divider which can be used in defuzzifier block for fuzzy logic controllers (FLC) to realize the weighted average and the weighted sum methods of the centroid strategy. This analog multiplier/divider is composed of two parts; it means that multiplication and division operations are performed by two separated circuits. Multiplication operation is carried out by a four-quadrant current-mode multiplier which was proposed in [28]. A squarer cell comprised of two saturated transistors is the core cell of the multiplier circuit. Division operation is accomplished by a circuit which works based on trans-linear (TL) principle. At first, TL principle was applied to bipolar transistors. Afterwards, Seevinck and Wiegerink extended it to MOS transistors [29]. The circuits are designed in 0.18μm CMOS technology under voltage supply of 2 Volt. The performance of proposed multiplier/divider is characterized through HSPICE simulations and its functionality in the defuzzifier block of a typical (3×3) FLC was examined. Various simulation results prove that, in addition to merits like suitable operation speed and power consumption, high precision can be cited as the main advantage of the proposed multiplier/divider.

2 Functional description

Among the various inference methods reported in the literature, the singleton or zero-order Sugeno’s method is very adequate for hardware implementation and more reliable method to guarantee an efficient control [30, 31, 30, 31]. For this method, the centroid is the most popular strategy among diverse defuzzification strategies. The centroid strategy can be performed in two styles: weighted average [22 , 30–32] and weighted sum [33, 34]. Their equations can be expressed as follows, respectively. $C = \frac{\sum_{i = 1}^{n} μ i \times si}{\sum_{i = 1}^{n} μ i}$ (1)

And $C = \frac{\sum_{i = 1}^{n} μ i \times si}{X}$ (2) where n is the number of quantization levels in the consequent part, μi and si are the firing degree and singleton values related to ith rule. In Equation 2, X is a constant value (e.g. 1).

2.1 Circuit description

2.1.1 Proposed Current-mode squarer circuit

It is obvious that, to actualize the nominator of Equations (1) and (2) a multiplier is required. Our proposed multiplier which was thoroughly described in [28] works based on a current-mode squarer cell illustrated in Fig. 1. In this circuit both of M1 and M2 are in the saturation region and a constant current passes through M1 (Ibias). The current of M2 is given by $Io = K_{2} {(V_{B} - V_{t 2})}^{2}$ (3) where K = 0.5μ COX (W/L) is transconductance parameter of transistor, μ is the electron mobility, COX is the gate oxide capacitance per unit area, W/L is the transistor aspect ratio, V _B and V _t2 are gate to source and threshold voltage of transistor M2.

Iin is the current input signal and Ibias is a suitable constant current which sets the initial voltage of node B (V ₀ when Iin = 0). V _E is an indicator for the deference between initial voltage of node B and the threshold voltage of M2. The voltage of node B is $V_{B} = R (Iin + Ibias) + V_{t 1} + \sqrt{\frac{2 Ibias}{K 1}}$ (4) $V_{0} = RIbias + V_{t 1} + \sqrt{\frac{2 Ibias}{K 1}}$ (5) $V_{E} = V_{0} - V_{t 2}$ (6)

Based on these equations, Equation (3) will change into Equation (7). $Io = k {(RIin + V_{0} - V_{t 2})}^{2} = k {(RIin + V_{E})}^{2}$ (7)

2.2.2 Multiplier circuit

Figure 2 shows that the structure of multiplier includes four numbers of the squarer cells. Consider I _x + I _y, - (I _X + I _Y) , (I _X - I _Y) and - (I _X - I _Y) as the input currents of the squarer cells, their output currents will be $Io 1 = k {(R (I_{X} + I_{Y}) + V_{E})}^{2}$ (8) $Io 2 = k {(- R (I_{X} + I_{Y}) + V_{E})}^{2}$ (9) $Io 3 = k {(R (I_{X} - I_{Y}) + V_{E})}^{2}$ (10) $Io 4 = k {(- R (I_{X} - I_{Y}) + V_{E})}^{2}$ (11)

Now, subtracting the summation of Io1 and Io2 from the summation of Io3 and Io4 will result $Iout = (Io 1 + Io 2) - (Io 3 + Io 4) = 8 {kR}^{2} I_{X} I_{Y}$ (12)

2.1.3 Squarer/divider circuit

Figure 3 shows the circuit of the proposed squarer/divider. This circuit has two current input signals, one of them takes part in producing the numerator current (I _num) and the other one in the denominator current (I _den). This circuit works based on the trans-linear principle. By employing this method, the squarer/divider characteristic of saturated MOS transistors will be available. In this circuit, an up-down trans-linear loop constructed by four transistors (i.e. M1, M3, M5 and M7) is used. The transconductance parameters of these MOS transistors are equal (i.e. K1 = K3 = K5 = K7 = K). Therefore, the KVL equation in this loop can be expressed as in Equation (13) $V_{gs 1} + V_{gs 5} = V_{gs 3} + V_{gs 7}$ (13)

Due to operating in saturation region and using equal transconductance parameters we have $\sqrt{I_{1}} + \sqrt{I_{5}} = \sqrt{I_{3}} + \sqrt{I_{7}}$ (14)

By squaring the both sides of Equation (14) Equation (15) will be derived. $I_{1} + I_{5} + 2 \sqrt{I_{1} I_{5}} = I_{3} + I_{7} + 2 \sqrt{I_{3} I_{7}}$ (15)

With respect to Fig. 3, I ₁ and I ₅ are equal to I _z and I _out, respectively. By assuming that I _M3 = I _M7 = I, Equation (15) can be rewritten as follows $2 I = \sqrt{I_{z} I_{out}} + \frac{I_{z} + I_{out}}{2}$ (16)

The KCL equation at node A can be written as follows $I_{z} + I_{M 3} + I_{M 5} = I_{z} + I_{M 5} + I_{M 7}$ (17)

So $I_{M 3} = I_{M 7} = I$ (18)

As a result, the assumption in Equation (16) is valid. On the other hand, by applying KCL at node C it is found that the addition of I _M3 and I _M7 is equal to $2 I = Iin + \frac{I_{z} + I_{out}}{2}$ (19)

Consequently, according to Equations (16 and 19) the output current of the squarer/divider circuit is $I_{out} = \frac{{Iin}^{2}}{I_{z}}$ (20)

1.1.4 Multiplier/divider circuit

By attaching the multiplier circuit to the squarer/divider circuit, the circuit of the proposed multiplier/divider will be obtained. The block diagram of the proposed multiplier/divider, which clearly describes the order of signal processing from input to output, is depicted in Fig. 4. Based on this scheme, for implementing a multiplier/divider circuit, two multipliers and two squarer/dividers are required. It is obvious that, the proposed circuit has a symmetrical structure which strengthens the linearity of the output current and makes it more accurate. I _X, I _Y and I _Z are variable input signals while both of I _b and I _c are constant currents (I _b = 5μA and I _c = 10μA) which determine the gain of the circuit. In Fig. 4 the positive and the negative signs indicate the directions of the applied currents to the circuit. As mentioned, the squarer/divider circuit has two input currents; one appears in the numerator and the other one in the denominator of the output current. Both of these currents are provided by multipliers. The denominator current is equal for both of the utilized squarer/dividers and it is produced by multiplier 2.

Thus, according to Equation (12), it can be expressed as follows $I_{den 1, 2} = 2 β I_{c} I_{z}, β = 8 {kR}^{2}$ (21)

In contrast, the numerator currents are different and can be defined as follows, respectively. $I_{num 1} = I_{b} + β I_{x} I_{y}$ (22) $I_{num 2} = I_{b} - β I_{x} I_{y}$ (23)

Substituting Equations (21–23) in Equation (20), will result $I_{out 1} = \frac{{(I_{num 1})}^{2}}{I_{den 1}} = \frac{I_{b}^{2} + 2 β I_{b} I_{x} I_{y} + β^{2} I_{x}^{2} I_{y}^{2}}{2 β I_{c} I_{z}}$ (24) $I_{out 2} = \frac{{(I_{num 2})}^{2}}{I_{den 2}} = \frac{I_{b}^{2} - 2 β I_{b} I_{x} I_{y} + β^{2} I_{x}^{2} I_{y}^{2}}{2 β I_{c} I_{z}}$ (25)

The output current of multiplier/divider will be obtained by subtraction of Equations (24) and (25). This subtraction is accomplished by a NMOS current mirror so that M14 in squarer/divider 2 and 1 is connected to the input and output of this current mirror, respectively. $I_{out} = I_{out 1} - I_{out 2} = \frac{2 I_{b} I_{x} I_{y}}{I_{c} I_{z}} = α \frac{I_{x} I_{y}}{I_{z}}, α = \frac{2 I_{b}}{I_{c}}$ (26)

Proportional to I _b and I _c, α is 1. As a result, we have $I_{out} = \frac{I_{x} I_{y}}{I_{z}}$ (27)

3 Simulation results

In this section, to validate the utility of the proposed multiplier/divider, various kinds of simulations were performed using HSPICE with 0.18μm CMOS parameters. The power supply voltage (Vdd) is 2 Volt. The aspect ratios of transistors are reported in Table 1 for both of circuits. The performance of the proposed circuit was defined by mathematical equations within the last section, but the used equations are approximate equations. So, the actual results wouldn’t follow the ideal results calculated by mathematical equations, exactly. Therefore, a deviation usually appears between ideal and real outputs which is referred as circuit error. In this work, the whole circuit consists of two parts where each part has its own error. To reduce the whole deviation, we attempted to compensate the error of each part by means of the other part error. Whereas the main error is caused by squarer/divider, to compensate its error we have to create a contrary error in the multiplier circuit, intentionally. To do this purpose, multiplier 1 and 2 are slightly different from each other so that in multiplier 2 the aspect ratio of M2, M3, M6 and M7 is (1/2) instead of (1.2/2). Moreover, in multiplier circuits the bias currents are 1μA and 1.2μA, respectively. All utilized resistors are 12 kΩ.

As discussed, the proposed circuit has three input currents I _X, I _Y and I _Z. To study the DC characteristic of the circuit, one of inputs is continuously swept and the other input varies discretely with specific step size, meanwhile the third input is constant. Figure 5 displays the multiplying ability of the circuit when I _X sweeps from −10μA to 10μA continuously, I _Y steps from −10μA to 10μA with 0.5μA step size and I _Z is fixed in 5μA. Figure 5b indicates that the nonlinearity error of the multiplication is less than 1% of the full scale output rang (40μA). The dividing ability can be examined whenever I _Z is swept from 5μA to 20μA continuously, I _X is varied from −10μA to 10μA with 0.5μA step size and I _Y is 10μA. Figure 6 illustrates the output current and its corresponding error where the nonlinearity error is less than 1% . To survey the multiplying and dividing ability concurrently, I _X sweeps from −10μA to 10μA continuously, I _Z steps from 5μA to 20μA with 1μA step size and I _Y is 10μA. The obtained result is depicted in Fig. 7 while the relative error is less than 1% . The drained currents from VDD which are shown in Fig. 8 clarify that, the maximum power dissipation is 626μW when I _X = I _Y = 10μA and I _z = 20μA (the drained current is 313μA). However, the quiescent power consumption is 278μW when I _X = I _Y = 0μA and I _z = 5μA (the drained current is 139μA). The frequency characteristic of the proposed multiplier/divider is shown in Fig. 9 where I _Y and I _Z are set to 10μA and 5μA, respectively while I _X is an AC-varying signal with a magnitude of 10μA. Based on Fig. 9, the –3 dB bandwidth is 21.5 MHz. To characterize the ability of the proposed circuit as a real time signal processing system, transient simulations were performed.

Figure 10 shows the pulse response of the multiplier/divider where I _Y and I _Z are set to 10μA and 5μA, respectively. I _X is a square pulse with an amplitude of 10μA and the frequency of 0.5 MHz. Proportional to the variation of I _X the settling times are 50.7 ns and 45.1 ns for the rising and falling edges. It means that the operation speed of this circuit is about 20 MHz. Therefore, whenever it is used in defuzzifier block, it will restrict the inference speed of the total fuzzy logic controller to 20MFLIPS in its turn. With respect to the obtained inference speed, the defuzzifier block can be readily considered as a real time signal processing system. Now, assume that all of the input currents are varying signals as shown in Fig. 11a, b displays the output current and its relative error. It can be observed that, similar to the DC simulations, the tracking error of the output current is less than 1% in the transient simulation too.

Eventually, to demonstrate the functionality of the proposed multiplier/divider in defuzzifier block, it was employed in defuzzifing block of a typical (3 × 3) fuzzy logic controller (FLC) which its block diagram is depicted in Fig. 12. According to FLC structure, for both inputs the universe of discourse is partitioned into three fuzzy sets similarly. Hence, the total number of required rules is nine. Circuitry, the fuzzy value of 1 is corresponding to 10μA.

The utilized singletons and triangular membership functions are shown in Figs. 13 and 14, respectively. For defined membership functions and singletons, the ideal control surface was obtained from fuzzy tool box of MATLAB software for both weighted average and weighted sum defuzzification methods. Based on Equation (1), in weighted average method the denominator current is the aggregation of currents originated from inference block (i.e. min circuits) as shown in Fig. 12. Figure 15 illustrates the normalized ideal and simulated control surfaces and the relative error. The simulated surface is obtained while each input of the controller is partitioned into 101 steps. Under this condition, RMS error is 1.08% of the full scale output. This error is less than the errors 2.3% and 2.7% cited in [15, 30].

However, some other works have calculated the RMS error while the inputs are partitioned into 11 steps. For similar condition, the RMS error is 0.37% which is much less than the reported errors 1.32% and 1.3% in [32, 34]. As described before, unlike the former method, in weighted sum method the denominator current is fixed in a constant value. For this method the normalized ideal and simulated control surfaces and the relative error are shown in Fig.16. In this case, the RMS error is 1.53% of the full scale output.

4 Conclusion

In this paper, a newly designed analog multiplier/divider was proposed to realize the centroid strategy of defuzzification in fuzzy logic controlling systems. The static and dynamic behavior of the proposed circuit was studied by performing various kinds of DC and transient simulations which certify the proper performance of this circuit. Yielded results exhibit the high precision of the control surfaces whenever the proposed circuit was employed in defuzzifier block. The layout of this circuit which is depicted in Fig. 17 has been drawn by Cadence Virtuoso software and illustrates that the occupied area is about 3024μm².

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