Design of real-time reconfigurable fuzzy logic controller with M-FRHC rule reduction technique

3.1 Fired rules hyper cube (FRHC)

The concept of using two overlapping MFs in rule reduction was proposed by Eichfled et al. in 1992 [42], but it was improvised in 1999 by I. Kalaykov and named as FRHC [18]. It is characterized by a layered parallel architecture of the fuzzy inference. Moreover, it reduces the dependency of processing time on number of inputs of the fuzzy system while dependency on the number of rules and fuzzy partitioning of all variables are completely eradicated [18]. [27, 28,43,44] has employed this scheme to enhance speed of their FLCs. However, this stipulation of two overlaps causes major worry in accuracy and tuning of the FLC, specially because the MFs cannot be unevenly distributed over the input spaces, which is circumstantial in majority of non-linear FLC system design.

3.2 Modified FRHC (M-FRHC)

FRHC rule selection method constraints the Rulebase design by limiting the number of membership operating over any part of the input region to two. But when this algorithm is applied to higher order non-linear systems, this affects system performance and tuning becomes extremely difficult [28, 45]. Thus to keep the simplicity of the FRHC intact while countering its major disadvantage, M-FRHC is proposed and incorporated it on system design.

Advantages of M-FRHC over its conventional counterpart can be understood considering a case where fuzzy logic antecedent MFs are as shown in Fig. 1. In the input space marked as X and Y, any input value will be fuzzified to more than two non-zero values since there are more than two overlapping MFs. Further it is observed that the number of non-zero values in a fuzzified input cannot exceed the number of overlapping MFs. If FRHC is applied on these set of input MFs, then useful data will be lost. FRHC will only return two non-zero fuzzy values in place of three if input lies in specified X or Y input space. This results in erroneous control output which is proportional to the weight of the discarded membership function and its implication on the Rulebase. Implementation of M-FRHC will allow the number of overlaps to vary suitable with conjunction to the complexity of the control system. Next section provides a comparative analysis of these two methods.

3.3 Analysis: Conventional FRHC and M-FRHC

Any generic FLC can be easily designed on the principles as stated by I. Kalaykov et al. [18] and depicted in Equation. (4). For all such FLCs, it can be observed that the computational complexity depend on N _cells which is non-linearly related to number of overlapping membership functions and number of system inputs as shown in Equation. (3). N cells = O n(3) where O represents number of overlaps considered and n represents number of inputs. This shows that N _cells increases exponentially with respect to the n. For systems implemented on platform of FRHC, the basic model provided by I. Kalaykov et al. [18] is as follows.

y = y aggr . ( y w - 1 )(4) where y aggr = ∑ i = 1 N cells w i . y i(5)y w = ∑ i = 1 N cells w i(6) and w _i represents the non-zero weights of the fuzzified input and y _i represents the Kernel of a output fuzzy set fired by the Rulebase.

However, the system assumes O = 2 and [18] states that, “..uncertainty has to be on boundary between two fuzzy sets”. Hereby, FRHC assumes a set of values from first column of Table 2 depending on the system inputs. Now, if O is predefined, the generic FLC system assumes value of N _cells based on n and this remains static. The computational complexity increases linearly with increase in n. However, in this paper M-FRHC proposes to dynamically assume the number of overlaps. In the proposed FLC M-FRHC N _cells are defined as following

N cells = { 5 , ∀ n = 1 16 , ∀ n = 2 27 , ∀ n = 3 16 , ∀ n = 4

These values of N _cells are assumed such that the number of effective rules for every inference could be kept low without affecting accuracy of the system. This combination is found to be ideal for this system since, increasing number of inputs will have minimum effect on overall computation time and complexity. In summary, for any system which has a complex input MFs as shown in Fig. 1, FRHC will fail to produce any output. In those cases, FRHC can be replaced by proposed M-FRHC.

4.1 Generic FLC design

This paper presents a generic FLC system with M-FRHC rule reduction technique and its system parameters are tabulated in Table 3. Characteristics features of this architecture is as follows:

32 bit precision Input and Output is considered.

This controller is implemented on a TI C6748 DSP processor even though FPGA is most preferred platform for implementation of FLCs [14–16]. The major reasons are

DSP provides effecient implementation of multiplication and accumulation (MAC) and this helps COA implementation.

Collectively, for this architecture, DSPs were judicially selected over conventional FPGAs.

4.2 Data synchronization and communication

Throughout this implementation process, data synchronization and communication between user and the H-FLC is critical as it can be observed in Fig. 3. It shows how data communication has been achieved with the help of various control signals between, client, server and the HFLC. A web application provides a systematic user interface which collects data from authenticated users. The application waits for a new connection request on startup. On successful login, a user is presented with a web page containing four different tab-windows, each for basic parameters, information about inputs, outputs and Rulebase. In Fig. 3, operations like connections, login, parameter collection and communication with H-FLC through a server program are performed by the web application and are shaded in Light Grey.

When a user provides the fuzzy control parameters (FCP) data, the web application validates the entered data based on following protocols.

All MFs have properly defined co-ordinates within specified range of operation.

When the new parameters are validated, a server application is invoked which connects serially to the hardware board. The board first completes current execution and generates control signal. Then it acknowledges any incoming serial communication request and starts receiving and storing fuzzy parameters in the data memory. Sys/BIOS is widely used real time operating system for TI DSPs and has been used to take care of the multitasking of fuzzy processes.

4.3 Proposed system architecture

The proposed system architecture involves hardware-software co-design to present a complete reconfigurable FLC as shown in Fig. 4a and Fig. 4b. The WebUI in client server model represents the software and the driver layer to interface the H-FLC through serial port. The DSP hardware receives FCP data serially and stores them in predefined memory locations as shown in Table 4. These parameters which are, segregated in two categories namely Setup and Rulebase data. The driver layer in the H-FLC receives and acknowledges the data transmission. The WebUI is a web application that drives the proposed H-FLC storing FCP data in a file as shown in 1. It must be noted that the FCP file is generated deliberately in accordance with Matlab Fuzzy Inference System (FIS) file format to provide liberty to integrate a parameter data file generated using Matlab Fuzzy Logic Toolbox as well. Submitting the parameters triggers a desktop application that is native to the server. Objective of this program is to transmits the FCP from database to the H-FLC through serial communication. The FCP data is stored in the DSP board based according to the memory map provided in Table 4. FLC designed with M-FRHC rule reducing Inference Engine, operates on the inputs with these FCP data to provide desired control action. FCP data is segregated in two parts, Setup and Rulebase. Offset address 0000H to 00D6H in Table 4 shows the details of Setup parameters. Rulebase parameters appear in memory location 00D7H to 1D0CH which is reserved to store 2401 1  rules. Fuzzifier, inference engine and defuzzifier is programmed with information about the data and its memory location. With these information, fuzzifier transforms crisp inputs in fuzzy domain and a Mamdani inference engine, coupled with the Rulebase in the system memory produces fuzzy output. Defuzzifier transforms fuzzy output compiled by the inference engine back to crisp output. There are various types of defuzzifier but in majority of control simulations, centroid of area (COA) is most prominent.

5.1 Code implementation

TMS320C6748 DSP Development Kit (LCDK) was used as hardware platform to realize the proposed architecture. The design is programmed in C language, cross compiled using TI Code Composer Studio and implemented on TMS320C6748 as target DSP processor. This hardware platform is capable of accepting FCP file and can operate based on it. Detailed memory utilization of the built code is shown in Fig. 5. It can be observed that the code size acquires 66% of the SHRAM and its size is 131KB.

5.2 Hardware-in-loop (HIL) testing environment

WebUI is developed in ASP.NET with C# and deployed using Microsoft IIS-7. The Web Pages that serves to collect various information pertaining to parameters related to FLC from users are shown in Fig. 6. Web page in Fig. 6a presents the WebUI where, parameters like name, type, implication, aggregation, and method,or method and defuzzification type are defined. Web page in Fig. 6b accepts details of inputs and their MFs whereas Web page in Fig. 6c accepts details about outputs and their corresponding MFs. Web page in Fig. 6d accepts the Rulebase and stores all data in FCP file as mentioned in Appendix. On submission of this, the entered data are validated and invokes a server application for communication with the board. This WebUI can be accessed over Ethernet from a client system situated far away from the controller and plant (simulated model).

To provide proof of concept for proposed in Section 1, an experiment was carried out with an Intel Corei5-2400 3.1 GHz PC with 4GB memory operating as a server with the WebUI. It is available to all the clients in the local network over same gateway. Authenticated user puts FCP data in a text file located in the server. This FCP data is used by H-FLC to generate control signal. The plant model is developed in Matlab and communicates with the H-FLC for controller I/O data exchange. The HIL test is shown in Fig. 7 and it is conducted as following:

Generation of I/O dataset from Simulink model using PID controller and FLC.

5.3 Armature controlled DC motor

A Simulink model to simulate Speed Control of a DC Motor with PID and Fuzzy Logic Controllers is put to use in this simulation experiment [46, 47]. The Simulink model shown in Fig. 8 uses a DC Motor with Armature Resistance (R _A ) = 1 Ω, Armature Inductance (L _A ) = 0.5, Inertia (J _M ) = 0.01, Damping (B _M ) = 0.1, Torque Constant (K _τ ) = 0.01 Nm/A and Back EMF Constant (K _B ) = 0.01 Vs/rad. Transfer function of the plant model is stated in Equation. (7). It is controlled by FLC and PID controllers in different datapaths. Simulation of this model produces the I/O dataset and is saved in a file which concludes first phase of this experiment. The data set consists of two inputs, error in speed and its derivative, and the control signal (voltage to the DC Motor) as an output.

θ ( s ) V A ( s ) = K τ L A J M s 3 + ( R A J M + L A B M ) s 2 × 1 ( K τ K B + R A B M ) s(7)

HIL test was performed as mention in This was compared to the Matlab output where an error of 2% was recorded. This simulation experiment was found to work seamlessly but, the hardware realization of this application was necessary to determine if this approach is perceivable in real-time.

6.1 Control output

The simulation output for the Simulink model in Fig. 8 is presented in Fig. 9a. The inputs and corresponding output was recorded and saved in file which is intended to be used as data source. The same FCP file used in this simulation was loaded in the FLC based DSP hardware through the server application. A separate Windows application was created to read the input data stored in the data source file and send it to the H-FLCexternally.

The H-FLC received the inputs and generated suitable control outputs which was sent back to the PC and recorded in a loop. The recorded data is then compared to actual simulated output for data validation. The time elapsed in this entire process has also been recorded. The inferences observed during this experiment has been tabulated in Table 5.

There were total of 100021 input samples in this entire simulation. Control signals generated from the simulation and H-FLC was recorded for each input samples and plotted in Fig. 9a. This plot validates that the control data output from the H-FLC is in synchronization with the simulated result with MSE of 2% . This deviation observed in control output of the H-FLC and Simulink simulation is because the design implements a vertices based approach to calculate COA as in (8). Popular way to compute COA is by implementing integral of area under a curve. Since this method is computationally resource intensive, it has been avoided. The vertices produced when fuzzy output is projected over output MFs as shown in Fig. 10 (in this figure, fuzzy output is assumed to be [0, 0.4, 0.6, 0.5]) are calculated and used in (8) for COA computation.

COA = 1 6 A ∑ i = 0 n - 1 ( y i + y i + 1 ) ( x i y i + 1 - x i + 1 y i )(8)

Where n represents number of vertices and

A = 1 2 ∑ i = 0 n - 1 ( x i · y i + 1 - x i + 1 · y i )(9)

The system has also been tested for its inference time. Inference time is defined as the time taken for a set of input to propagate to the output and produce a control action. Fig. 9b provides no observation related to the execution time of the H-FLC. Thereby, time elapsed in the entire process of testing with 100021 samples was also been recorded. It found to be 7.248949 seconds for entire process and on average 0.073 ms or 73 μs for single inference. This data provides an estimate of the inference time that can be achieved with the proposed H-FLC. However it is should to be noted that this time does not include any instance where parameters have tuned in between the process. Next Section analyze the influence of parameter loading in run-time using some more benchmark control problems used widely in literature.

6.3 Validation of the proposed system

This Section investigates the applicability of the proposed H-FLC to various system models and analyze its performance with respect to inference time and control output separately. Some benchmark control problems are used to test the applicability and generality of the proposed controller, namely Two Tank Water Level Controller [47], Intelligent Cruise Control [48], first order system with dead time for anti-windup scheme in PID [49]. All these system models have been implemented on Simulink and they are available in Mathworks File Exchange repository. Most of these models are controlled using PI/PD/PID controllers. But for validation of the system, these PID controllers are replaced by suitable FLCs generated in simulation environment of Matlab/Simulink. The process is followed by validation of the H-FLC and is executed in similar manner as elaborated in Section 1. The proposed system is similarly tested for performance and their analysis is tabulated in Table 6. The details of their corresponding HIL test as described earlier is provided in Fig. 11.

In the Table 6, findings on the cycle time provides an insight over the design. The system was observed to perform at better cycle time when the dataset used for testing contained large number of data samples. This notion requires further investigation to unravel the dependency of FCP data extraction time on overall execution cycle. Hereby to determinate the minimum FzLOPS that can be obtained using this device, it is necessary to perform this experiment with lower number of data samples (in this case authors reduced the data samples by a factor of 100). It is observed that there exists around 0.3 ms delay for every iteration of parameter extraction. However the effects of larger dataset reduces the average inference time. The results obtained from this set of HIL test is shown in Table 7. The minimum FzLOPS obtained depicts that the system operates on a cycle time of at least 4.5 KFzLOPS or 0.22ms per operation. It should be noted that the reduced number of samples are same as the primary dataset which was used in Table 6 and both shall render same error. However, MSE may or may not remain same, depending on the reduced samples that were used for the experiment. Therefore, MSE is an insignificant parameter for this experiment and it has been discarded in Table 7.

6.4 Comparative analysis to existing works

The H-FLCS design is implemented on a programmable DSP. There are few works reported in the literature which implements similar designs on FPGA platform. However, these systems provide fewer flexible FCP features in comparison to the proposed design. The performance of the proposed H-FLCS was compared to the existing FPGA based designs presented in [40, 50]. A summary of these designs are tabulated in Table 8. It can be observed that the proposed G-FLCS design provides variety of features with adequate speed and flexibility in comparison to the FLCS designs reported in [40, 50]. This design provides a top speed of approximately 13 KFLIPS for a 2-input 1-output system with 49 rules with seven MFs for each input and output. The proposed design also support a maximum 4-input 1-output system with seven MFs for each input and output space. This adds up to a total of 2401 rule system. The code size of 66 % reported in Fig. 5 implements 4-input 1-output system. Unlike the other systems, the proposed design also works with different types of output membership function.

There is also a [26] FPGA based design of a scalable FLC proposed by Sun et. al. in similar line of approach. This is an elegant and extremely fast design. The design claims to achieve a top speed of 25 MFLIPS. However, it implements LUT based design. In LUT based designs, the resolution of the input output signals and the membership functions are generally low. Moreover, this design only supports triangular membership functions which cannot be reprogrammed. In this design, the input, output and membership function accuracy ranges between 2 to 16 bits. Moreover, this design do not support runtime FCP configuration. In the proposed H-FLC design however, a resolution of 32-bit for I/O and membership functions is achieved. Moreover, the FCP in the proposed design can also be remotely programmed on run-time and it also includes singleton, triangular, trapezoidal, Gaussian and GBell membership functions.