Design an optimized rectifier with TLBO based on threshold voltage cancellation technique

Abstract

In this paper a full wave rectifier is presented for RFID passive tags working at 960 MHz frequency. For designing the rectifier multi-stage structure, which has high sensitivity and efficiency, is used for the low amplitude input voltage. In order to eliminate the effect of pass transistors threshold voltage, bootstrap circuit which has cross coupled structure is utilized. For optimizing power conversion efficiency (PCE) and gaining high output voltage from the low input voltage the size of the elements and number of stages are modeled and optimized with neural network and TLBO algorithm, respectively. Due to the achieved results from the TLBO algorithm 6 stages are considered for the rectifier designing. For the low input voltage 0.6 V, the power conversion efficiency and the output DC voltage are achieved 50.8% and 1.52 V, respectively. The simulation of the proposed rectifier is done with Cadence software in 0.18μm CMOS technology and its layout equals to 0.00525mm².

Keywords

Vth cancellation technique rectifier TLBO PCE

1 Introduction

The application of the radio frequency identification (RFID) becomes more common in industries and sciences and recently is more developed [1]. Using electromagnetic waves in the range of UHF causes more sensitivity and the distance between the tag and reader. Also for decreasing the costs and increasing the lifetime passive tag is used. The passive tag can be supplied its energy from the received electromagnetic waves [2 –4]. The received power from the reader is limited thus the design of high efficiency rectifier is the important challenge. For rectifying the received waves usually the CMOS bridge structure or the Dickson rectifier are used. The block diagram of the passive tag is shown in Fig. 1.

The received waves from the tag antenna of the rectifier change into the DC voltage and the required voltage of the tag is provided. One of the common disadvantages of the rectifier is the output drop voltage because of the threshold voltage of the transistors that not only reduces the output voltage but also decreases the power efficiency.

The Schottky diodes which have lower drop voltage can be employed for the rectifying [5 –7]. As the Schottky diodes aren’t compatible with the standard CMOS technology, they need more masking process and cost of fabrication. In order to eliminate the effect of threshold voltage the circuit which distributes the battery voltage to the rectifier stages has been presented in [8]. Also in [9] the circuit for decreasing the inner threshold voltage has been proposed. In [10] the cross-coupled structure is used which shows only one drop of threshold voltage from the input voltage source at the output voltage. The circuit with the bootstrap structure has been presented in [11] in order to eliminate the threshold voltage of the pass transistors. The full wave rectifier with the bootstrap circuit and cross-coupled structure is presented in [12] for omitting the threshold voltage of the pass transistors that not only ameliorates the efficiency but also increases the output voltage. The multi-stage rectifier which reduces the leakage current of the body with the help of body biasing has been proposed in [13].

Fig.1

The block diagram of the passive tag.

In this paper the full wave rectifier is proposed with the aim of eliminating the effect of threshold voltage of the pass transistors for the RFID passive tags at UHF frequency. In the rectifier the cross-coupled structure is used for the NMOS pass transistors while the capacitor and the transistor as the bootstrap circuit are used for omitting the effect of PMOS pass transistors threshold voltage. In addition, the multi-stage rectifier is employed to increase the output voltage. The sizes of the element and also the number of stages are set with the neural network and TLBO algorithm to optimize the power efficiency and reach the highest output voltage from the low amplitude input voltage. This paper is organized as follows: the novel topology of the full-wave rectifier and multi-stage rectifier is presented in section 2. The neural network and TLBO algorithm for modeling the circuit and gaining the optimized results of the multi-stage circuit are described in section 3. The simulation results of the proposed rectifier and the conclusion are presented in section 4.

2 The proposed rectifier

The full wave rectifier design which is inspired from the cross-coupled structure and bootstrap circuit is shown in Fig. 2. It works at 960 MHz frequency and is presented with the aim of improved efficiency. In this rectifier transistors M₁-M₄ are replaced the diode connected transistors of the bridge rectifier and conduct the current from the input source to the output load.

Fig.2

The full wave rectifier with cross-coupled structure and bootstrap circuit.

Transistors M₁ and M₂ have the cross-coupled structure to decrease the channel resistance at the time of activating. In order to improve the efficiency and increase the output voltage the bootstrap circuit which omits the effect of threshold voltage of the PMOS pass transistors is used. Transistor M₇ with C_B capacitor makes the bootstrap circuit. In this structure the gates of transistors M₃ and M₄ are connected to each other and M₇ the diode connected transistor which is placed between the gate of these two transistors and the output, can eliminate the effect of threshold voltage of PMOS pass transistors M₃ and M₄. At first the current of the input source charges the output capacitor and C_B capacitor from the diode connected transistors M₅ and M₆. The voltage of C_B can be efficient for the full conduction of pass transistors. The sizes of transistors M₅ and M₆ are selected smaller than those of pass transistors to reduce the leakage current.

In the positive half cycle when the input voltage (V_IN+) is higher than output voltage, the current charges the output capacitor from M₅, the diode connected transistor. The voltages of the output capacitor and C_B are achieved from Equations (1) and (2), respectively. $V_{OUT} = V_{IN} - | V_{th 5} |$ (1) $V_{B} = V_{OUT} - | V_{th 7} | = V_{IN} - | V_{th 5} | - | V_{th 7} |$ (2)

The voltage of V_B can activate the transistor M₃ to simultaneously charge the output capacitor with M₅ transistor. The voltage of V_SG(M3) is achieved from Equation (3). $V_{SG, M 3} = V_{IN} - V_{B}$ (3)

Due to the Equation (4), the transistor M₃ is deactivated when V_SG(M3) equals to its threshold voltage. $V_{IN} - V_{B} = | V_{th 3} |$ (4)

By using Equations (1 to 3) in Equation (4), the output voltage can be calculated from Equation (5). $V_{OUT} = V_{IN} - (| V_{th 3} | - | V_{th 7} |)$ (5)

Therefore, based on Equation (5), if |V_th3| = |V_th7|, the output capacitor charges to the equal value to the input voltage.

M₅ and M₆, PMOS diode connected transistors, work in dynamic region and their body isn’t connected to the highest voltage during the full cycle that leads to the leakage current of the body and the increment of the threshold voltage of the diode connected transistors. For omitting the effect of M₅ and M₆ threshold voltage transistors M₈-M₁₁ are employed. Since the effect of threshold voltage of M₃ and M₄ transistors is eliminated with bootstrap circuit, the body biasing circuit doesn’t perform for M₃ and M₄ in order to have the maximum output voltage, thus the body of these transistors is connected to V_OUT.

To decrease the parasitic capacitors of the pass transistors which work in 960 MHz and also for supplying the required current for the output load the sizes of the pass transistors M₁ to M₄ should be optimized. The widths of auxiliary transistors M₅ and M₆ that are responsible for charging the output capacitor and C_B initially should be chosen minimum to reduce the leakage current of this path. The transistors size of body biasing should be selected minimum.

When the distance between the tag and reader is long the received power from the tag antenna is so week that the one- stage rectifier can’t provide the required DC voltage. Therefore for increasing the output DC voltage for the low amplitude input voltage the multi-stage rectifier shown in Fig. 3 is proposed.

Fig.3

The proposed multi-stage rectifier.

To achieve the power conversion efficiency and gain the higher output DC voltage for the low input voltage in the multi-stage structure the size of elements is modeled with neural network and is optimized with TLBO algorithm.

3 The neural network and TLBO algorithm

For modeling the rectifier and making the connection between the inputs and output neural network is used. neural network provides the nonlinear mathematic function for multi-stage rectifier. The created function by the neural network is used in TLBO algorithm and the appropriate inputs for the desired output are achieved.

In order to optimize the power and gain the DC output voltage for the low input voltage of multi-stage structure, 6 inputs and 2 outputs based on Table 1 are considered. The widths of PMOS and NMOS pass transistors (W_n, W_p), the widths of transistor and the value of capacitor of bootstrap circuit (W_B, C_B), the amplitude of input voltage (V_in) and number of stages (N) are considered as inputs. The variations of inputs effect on the power conversion efficiency and output DC voltage as the output parameters. Increasing the value of coupling capacitor C_C leads to increasing the output voltage. To reduce the chip area this value should be confined.

Table 1
The inputs and outputs of the neural network

Input Output

(W) _NMOS (PCE) _output

(W) _PMOS (Vout)

(W) _Bootstrap

(C) _Bootstrap

(Vin)

(N)

Input	Output
(W) _NMOS	(PCE) _output
(W) _PMOS	(Vout)
(W) _Bootstrap
(C) _Bootstrap
(Vin)
(N)

3.1 The neural network

For producing the mathematic function perceptron neural network is used for modeling the rectifier. Figure 4 shows the one-layer perceptron network. The achieved mathematic function from the neural network defines the relation between the inputs and outputs. Neural network includes three steps such as normalizing, training the mathematic function and testing it. At first 100 simulations are done and the outputs are measured in each step. In the normalizing step the simulated data is set in the range of [1, 0]. Among such normalized data 70 data is considered for training the mathematic function and 30 data are used for testing the trained function.

Fig.4

One-layer perceptron network.

The applied mathematics function to the perceptron network is the logsig(x) that is placed between the hidden and output layer. This function is achieved from the Equations (6 and 7) for the hidden and output layers, respectively. $Y = log sig (Xu)$ (6) $Z = log sig (Yw)$ (7)

Where X is the normalized inputs, Y is the output of the hidden layer, Z is the outputs, u and w are the weights of hidden and output layers, respectively.

The perceptron network receives 70 normalized data related to the inputs and outputs and distinguishes the weight of hidden and output layer and consequently produces the nonlinear mathematic function. In the testing step the function is tested by the 30 normalized data in order to be sure about the integrity of the function. In this step the error of the mathematic function is measured and if the error is lower than 4% the function is used for TLBO algorithm.

3.2 TLBO algorithm

TLBO algorithm is one of the novel optimized techniques which are designed based on learning and teaching of students and teacher principles and due to learning and teaching engages in the optimization [14]. The TLBO algorithm flowchart is presented in Fig. 5. This algorithm uses the population of answers for achieving the total result. The population is the students of the class. The teacher tries hard to teach the students and improves their knowledge. The best member of the population is the teacher. Besides the teaching of the teacher, the communication between the students can play an important role in improving the knowledge of the class. Therefore the TLBO algorithm divides into two groups such as teacher phase and student phase. In the teacher phase, the teacher tries hard to change the knowledge of the students into his knowledge. This process is done randomly based on Equation (8) and produces the new member.

Fig.5

TLBO algorithm structure.

X_{new, i} = X_{old, i} + r_{i} (X_{tech, i} - T_{F} M_{i})

(8)

In this equation i index is the number of inputs, X_old,i is the old member of population, r_i is the random number between [1,0], X_tech,i is the best member (teacher), T_F is the teaching factor that its value is considered 1 or 2. M_i is the knowledge mean of students and X_new,i is the new member that is accepted if it is better than the old one.

In the student phase the students can improve their knowledge by exchanging their knowledge. This exchange is expressed by Equation (9). $X_{new, i} = X_{old, i} + r_{i} (X_{j} - X_{k})$ (9)

Where index i is the number of inputs, X_old,i is the old member of population, r_i is the random number in the range of [1,0], X_k and X_j are two students if f (X_j) > f (X_k) and j ≠ k, X_new,i is the new member that is accepted if it is better than the old one. In each cycle the new members are made that are considered as the new populations for the next process and this loop continues until the optimized result is found. Figure 5 shows this algorithm.

For achieving the most optimized power conversion efficiency and reaching the DC output voltage for the low input voltage, TLBO algorithm is used. The maximum and minimum inputs specified in Table 2 are used in TLBO algorithm. The range for these inputs is experimentally selected and in this range the appropriate outputs are achieved from the inputs.

Table 2

Maximum and minimum inputs specified used in TLBO algorithm

Input	Min	Max
(W) _NMOS	50μm	100μm
(W) _PMOS	60μm	120μm
(W) _Bootstrap	220nm	2.2μm
(C) _Bootstrap	2pF	4pF
(Vin)	0.55V	0.65V
(N)	3	8

The power conversion efficiency and the required DC output voltage is introduced to the algorithm. The initial population is randomly selected between the minimum and maximum inputs and based on the teacher and student phase the new population of inputs are achieved for the best output. The output is gained by adding the weight of power conversion efficiency and DC output voltage as Equation (10). $F = \sqrt{{(\frac{PCE}{40 %})}^{2} + {(\frac{Vout}{1.5})}^{2}}$ (10)

The power conversion efficiency (PCE) and the voltage conversion (VCE) ratio can be calculated as Equations (11 and 13). $PCE = \frac{P_{out (DC)}}{P_{in (RF)}} = \frac{V_{out}^{2}}{R_{L} * P_{in (RF)}}$ (11) $P_{in (RF)} = \frac{1}{T} \int_{0}^{T} V_{in} (t) * I_{IN} (t) dt$ (12) $VCE = \frac{V_{out (average)}}{| V_{in} |}$ (13)

This process continues until the most optimized power conversion efficiency and the maximum output voltage are achieved. Finally the most optimized inputs are achieved by TLBO algorithm.

4 The simulation results of neural network and TLBO algorithm

The proposed rectifier is simulated by Cadence software in TSMC 0.18μm CMOS technology at 960 MHz frequency. In this paper the output load and the capacitor load are considered 20kΩ and 1pF, respectively, as the resistance and capacitance load of next stages.

The error curve of trained function by the neural network is shown in Fig. 6.

The average and maximum error of trained function in testing process are presented in Table 3. The average error in testing process is lower than 3% which shows the correct working of function.

Fig.6

The error curve of trained function by the neural network.

Table 3

The average and maximum error of trained function in testing process

Output	Mean error (%)	Max error (%)
PCE	1.92	10.65
V_out	2.69	14.12

The achieved results of inputs by TLBO algorithm and the used values for each cell of the proposed multi-stage rectifier are presented in Table 4. L is considered 0.18μm for all of the transistors while the coupling capacitor is selected C_c = 10pF_(NMOS,cap).

Table 4

The achieved results of inputs by TLBO algorithm and the used values for multi-stage rectifier

Input	TLBO output	This work
(W) _NMOS	88.09μm	88μm
(W) _PMOS	101.84μm	102μm
(W) _Bootstrap	641.1nm	640nm
(C) _Bootstrap	2.89pF	2.9pF
(Vin)	0.597V	0.6V
(N)	6.133	6

The output voltage of different stages of the optimized 6-stage rectifier versus the time is shown in Fig. 7. By considering the inputs based on Table 4 the DC output voltage is 1.52 V and the output ripple is ±7 mV. The output voltage is appropriately selected that is suitable for the input of regulator.

The power conversion efficiency of the proposed 6-stage rectifier versus the input voltage is shown in Fig. 8. The power conversion efficiency is 50.8% at 0.6 V input voltage.

Figure 9 shows the DC output voltage of 6-stage versus the input voltage. The value of VCE is 42.2% at 960 MHz frequency and 0.6 V input voltage.

Fig.7

The output voltage of different stages of the optimized 6-stage rectifier.

Fig.8

The power conversion efficiency of the proposed six stage rectifier versus the input.

Fig.9

The DC output voltage of 6-stage rectifier versus the input voltage.

Figure 10 shows the chip area of the proposed 6-stage rectifier which equals to 275×300μm² in 0.18μm CMOS technology.

Fig.10

The layout of the designed rectifier.

The comparison of the proposed 6-stage rectifier with the other rectifiers is presented in Table 5. At the UHF frequency the proposed multi-stage rectifier, which has the optimized dimension and number of stages with the help of TLBO algorithm, has the best power conversion efficiency. Since the most tag blocks such as regulator work with 1.5 V voltage the output voltage for the low input voltage is suitable for the input of regulator.

Table 5

The comparison of the optimized charge pump converter with the other charge pumps

Reference	Frequency	Technology	Number	Size	V_in (V) &	V_out	R_Load &	η
	(MHz)	(μm)	of stages	(μm2)	P_in(dBm)	(V)	C_Load	(%)
[13]	900	0.18	3	–	V_in= 0.8–1.8	5.02	20kΩ	30
[15]	950	0.3	6	800*800	P_in= –14	1.5	I_Load= 0.4μA	1.2
[16]	900	0.35	–	780*490	P_in= –14.7	1.52	500kΩ	13
This work	960	0.18	6	275*300	V_in= 0.6	1.52	20kΩ &1pF	50.8

5 Conclusion

In this paper the full wave rectifier for UHF frequency is presented by the aim of eliminating the threshold voltage of pass transistors. The rectifier uses the bootstrap circuit with the cross- coupled structure in order to omit the threshold voltage. For low amplitude of input voltages the multi-stage rectifier is used. To increase the power conversion efficiency and reach the maximum output voltage the size of elements and number of stages are optimized by TLBO algorithm. The rectifier is simulated in 0.18μm CMOS technology and its layout equals to 0.00525mm². At 960MHz operational frequency and 0.6V input voltage and 20kΩ load the power conversion efficiency and DC output voltage of the proposed 6-stage rectifier are 50.8% and 1.52V, respectively.

References

Han

, Lim

H.S.

and Lee

J.M.

An efficient localization scheme for a differential-driving mobile robot based on RFID system, IEEE Transaction 54(6) (2007), 3362–3369.

Salehi

M.R.

, Dastanian

, Abiri

and Nejadhasan

A 1.58 nW power consumption and 34.45 ppm/° C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag, Microelectronics Journal 46(5) (2015), 383–389.

Salehi

M.R.

, Dastanian

, Abiri

and Nejadhasan

A 147μW, 0.8 V and 7.5 (mV/V) LIR regulator for UHF RFID application, AEU-International Journal of Electronics and Communications 69(1) (2015), 133–140.

Salehi

M.R.

, Dastanian

, Abiri

and Akbari

A strategy to improve the charge pump voltage conversion ratio for RFID passive tag, International Journal of Electronics Letters (2015). DOI: 10.1080/21681724.2015.1036798.

Karthaus

and Fischer

Fully integrated passive UHF RFID transponder IC with 16.7-μW minimum RF input power, IEEE Journal of Solid- State Circuits 38(10) (2003), 1602–1608.

Theilmann

, Presti

, Kelly

and Asbeck

Near zero turn-on voltage high-efficiency UHF RFID rectifier in silicon-on-sapphire CMOS, Proceedings of IEEE RFIC (2010), 105–108.

Tran

, Lee

and Lee

Development of long-range UHF-band RFID tag chip using Schottky diodes in standard CMOS technology, Proceedings of IEEE RFIC Symposium (2007), 281–284.

Tran

and Lee

J.W.

Simple high-sensitivity voltage multiplier for UHF-band semi-passive radio frequency identification tags using a standard CMOS process, IET Microwaves, Antennas & Propagation 4(11) (2010), 1974–1979.

Nakamoto

et al., A passive UHF RF identification CMOS tag IC using ferroelectric RAM in 0.35-um technology, IEEE Journal of Solid-State Circuits 42(1) (2007), 101–110.

10.

Rakers

et al., Secure contactless Smartcard ASIC with DPA protection, IEEE Journal of Solid-State Circuits 36(3) (2001), 559–565.

11.

et al., Piezoelectric micro-power generation interface circuits, IEEE Jourbal of Solid-State Circuits 41(6) (2006), 1411–1420.

12.

Hashemi

, Sawan

and Savaria

A High-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices, IEEE Transaction on Biomedical Circuits and Systems 6(6) (2012), 326–335.

13.

Sheng

L.D.

, Cheng

Z.X.

, Kui

, Zheng

L.S.

, Mei

H.X.

, Yao

and Ling

T.Q.

New design of RF rectifier for passive UHF RFID transponders, Microelectronics Journal 41(1) (2010), 51–55.

14.

Rao

R.V.

, Savsani

V.J.

and Vakharia

D.P.

Teaching–learning-based optimization: A novel method for constrained mechanical design optimization problems, Computer-Aided Design 43(3) (2011), 303–315.

15.

Umeda

, Yoshida

, Sekine

, Fujita

, Suzuki

and Otaka

A 950-MHz rectifier circuit for sensor network tags with 10-m distance, IEEE Journal of Solid-State Circuits 41(1) (2006), 35–41.

16.

Yao

, Wu

, Shi

and Dai

F.F.

A Fully integrated 900-MHz passive RFID transponder front end with novel zero-threshold RF–DC rectifier, IEEE Transactions on Industrial Electronics 56(7) (2009), 2317–2325.

Design an optimized rectifier with TLBO based on threshold voltage cancellation technique

Abstract

Keywords

1 Introduction

Table 1 The inputs and outputs of the neural network Input Output (W) NMOS (PCE) output (W) PMOS (Vout) (W) Bootstrap (C) Bootstrap (Vin) (N)

References

Table 1
The inputs and outputs of the neural network

Input Output

(W) _NMOS (PCE) _output

(W) _PMOS (Vout)

(W) _Bootstrap

(C) _Bootstrap

(Vin)

(N)