Constant voltage/current with slowly rising control for high power DC-DC converter based on FPGA digital control

Abstract

In this paper, a hill-climbing method is adopted to control the output of full bridge circuit to achieve desired constant voltage/current output. A novel technology also is presented to control the rising time of the DC converter output. The hardware implementation of this digital control is based on the Field Programmable Gate Array (FPGA) digital chip. The proposed hill-climbing control algorithm can automatically adjust the Pulse Width Modulation (PWM) control parameter to handle the DC converter output approaching desired one. High frequency power supply with DC switching circuit has been paying more attention to its small size, light weight, and small electromagnetic interference. Digital control has many different control modes than continuous circuit one, and digital control can be updated at any control mode, unlike continuous circuit design cannot be changed once it is completed. That is, the merit of digital control is flexible and programmable which is why the FPGA digital control used in this paper to control the DC switching circuit. We obtain the FPGA execution code by establishing its corresponding Matlab/Simulink simulation model. After meeting simulation test, the Matlab/Simulink model can be directly transformed into Hardware Description Language (HDL) code. This greatly saving the time of writing HDL code which often is a barrier to the electrical engineer. Finally, a high power, 7.2 KW, DC-DC converter experiment is presented to confirm the feasibility of the proposed control method and design procedure.

Keywords

Hill-climbing method full bridge circuit FPGA (Field Programmable Gate Array) digital control PWM (Pulse Width Modulation)

1. Introduction

Recently, due to the increasing demand for high-power DC converters, many research reports have been proposed [1 –6]. In the past, there were too many conductivity losses and overheating problems for a DC converter until that high frequency DC converter design with zero voltage switching [7 –11] was presented but its output power was not high enough. So middle tap transformer and full-wave rectifier were presented to deal with the high power problem. Conventional controller’s implementation typically was analogical controllers [3, 8] or digital micro-controllers [12, 13]. The main drawback of analog control is that the control flexibility is poor and the control mode is completely limited to the ready-made component IC. Analog control often requires a larger volume of analog control circuit so that the corresponding circuit size and cost is relatively higher than digital one.

Because the dynamics of the DC converter with control are both high order and nonlinear where dominant poles have a time constant below 0.3 ms. If use the general micro-controller which is a serial implementation of program, it is difficult to achieve “against the instant impedance changes to increase the relatively stable output voltage” under the DC-DC converter closed-loop system. Speeding up the processing of data is the direction of solving above mentioned problem. And so, the FPGA chip with parallel computing was used to solve this problem recently.

Digitalization is the recent development trend resulting that FPGA digital control is more and more adopted by industry because its instruction operation can be done in hardware parallel mechanism. In each clock cycle, FPGA with a parallel mechanism can complete more operations than the digital signal processing (DSP). The FPGA hardware cost is cheaper than the DSP one. And FPGA design is more flexibility. So more FPGA controller papers are proposed to implement different control mode [14, 15] owing to its fast parallel data computing functions and low hardware cost. This is why we present a hill-climbing control law based on the FPGA chip to handle the full-bridge circuit to obtain constant voltage/current output with a desired rising time. The proposed hill-climbing control is different from the traditional PID control for that the proposed control can automatically adjust the control parameters to achieve desired system performance rather than manually adjusting parameter of PID. It is somewhat similar to the iteration method and is an effective control application. This paper also presents a novel method to control the system output approaching desired one at the desired set time because high power DC converter with slowly rising output control is an indispensable feature for the electroplating factory.

This paper is organized as follows: The configuration of the full-bridge DC converter is viewable in Section 2. Section 3 proposes the digital design algorithm with a rising time interval set for a DC converter. A given experiment shows the proposed controller’s feasibility in Section 4. Conclusions are summarized in Section 5.

2. Problem formulation and characteristics

A full-bridge type of DC-DC high power converter with a center-tapped transformer is shown in Fig. 1 [16, 17]. The parameters in Fig. 1 are described as follows: input DC voltage V_in, output DC voltage V_o, output current i_o, R_s is a resistance referred as a shunt, purely for current measurement purpose. The coil ratio of the transformer primary and secondary side is N₁: N₂. Traditional phase-shifted PWM control to Fig. 1 is implemented by the hardware IC, not program writing IC, for completing constant voltage/current and zero voltage switching. The literature [18] has a detailed description of the above issues. The phase-shifted PWM technology in reference [18] can be plotted in Fig. 2 and summarized as belows:

Fig. 1.

Full-bridge DC converter with center-tapped transformer.

Fig. 2.

Phase-shifted PWM control.

(Q_A, Q_B) is a set of PWM square waves that are mutually opposite to each other with a fixed period T. The left and right edge time of Q_B high state waveform between the one of Q_A is Δt₁ in Fig. 2. This Δt₁ size affects the success or fail of zero voltage switching (soft switching).

(Q_C, Q_D) is a set of PWM square waves that are mutually opposite to each other with a fixed period T. Δt₂ is the time that Q_C high state of the left and right edge distances the one of Q_D wave in Fig. 2. The suitable Δt₂ is chosen, then the primary side of the transformer current will approach a constant value no jitter, that is called zero voltage switching (soft switching). That is, both Δt₁ and Δt₂ can affect soft switching ok or not.

The load output on the secondary side of the transformer depends on the length of the overlap Δt₄ between Q_A and Q_D. The overlap between Q_B and Q_C is also set as Δt₄. So, control the load output magnitude is equivalent to regulate the size Δt₄.

Since Q_C and Q_D are a dependent PWM square wave to each other. When Q_C and Q_D are simultaneously delayed by Δt₃ time, the Δt₄ size, the overlap between Q_A and Q_D, will be changed simultaneously.

In view of the above issues, the larger the Δt₃, the smaller the load voltage output obtains because the overlap amount Δt₄ becomes smaller. Tunning Δt₁ and Δt₂ can get soft switching (zero voltage output). The entire system circuit among FPGA digital chip, analog circuit, and power switching components can be shown in Fig. 3.

The output voltage V_o1 on the secondary side of the transformer in Fig. 1 mixed with the control PWM Fig. 2 can be expressed as

Fig. 3.

Relation between digital/analog circuit and power switching components Q_AQ_D.

$\begin{matrix} V_{o 1} = \frac{1}{T} \int_{0}^{T} V_{o 1} (t) dt = \frac{1}{T} (\int_{0}^{T} \frac{N_{2}}{N_{1}} * V_{in} (t) dt) \\ = \frac{1}{T} (\int_{0}^{Δ t_{4}} \frac{2 N_{2}}{N_{1}} * V_{in} (t) dt) \\ = \frac{2 N_{2}}{N_{1}} * \frac{Δ t_{4}}{T} * V_{in} \end{matrix}$ (1)

where $0 < Δ t_{4} < \frac{T}{2}$ and V_in is DC voltage. From Fig. 2, we know that the delay time Δt₃ is longer (shorter), the overlap time Δt₄ becomes shorter (longer). So the relation between Δt₃ and Δt₄ can be expressed as $Δ t_{4} = \frac{T}{2} - Δ t_{3}$ (2)

After substituting (2) into (1), we have $V_{o 1} = \frac{2 N_{2}}{N_{1}} * \frac{\frac{T}{2} - Δ t_{3}}{T} * V_{in} = \frac{N_{2}}{N_{1}} * (1 - \frac{2 Δ t_{3}}{T}) * V_{in} .$ (3)

By the Kirchhoff’s Voltage Law (KVL) law, the DC voltage on the secondary side of transformer can be written as $V_{o 1} = L_{O} \frac{{di}_{o}}{dt} + i_{o} R_{s} + V_{o} \approx i_{o} R_{s} + V_{o} ≜ V_{s} + V_{o} .$ (4)

Substituting (3) into (4) obtains $\frac{N_{2}}{N_{1}} * (1 - \frac{2 Δ t_{3}}{T}) * V_{in} = V_{s} + V_{o}$ (5)

where Δt₃ is regarded as the control input to produce four Q_A ∼ Q_D PWMs, like Fig. 2, such that the system output V_o approaches the desired constant voltage/current.

From (5) we know that the delay time Δt₃ can influce output voltage V_o and shunt voltage V_s that is proportional to output current i_o. Δt₃ can be adjusted for producing suitable four PWMs, like Fig. 2, to handle output voltage V_o to attain the desired one. This is regarded as a constant voltage control. On the other hand, if use Δt₃ to control shunt voltage V_s to obtain the desired current output i_o then the control law is said constant current control. The magnitude of load voltage V_o and current output i_o shown in Fig. 1 is controlled by the delay time Δt₃. That is, when the input Δt₃ is small (large), then V_o and i_o are large (small). Based on the above discussion, this paper addresses the following issues:

Constant voltage (CV) design V_o ≅ V_r: Design a hill-climbing control in Fig. 7 to adjust the parameter Δt₃ so that the load output voltage V_o approaches the reference V_r via the feedback signal V_o;

Constant current (CC) design $i_{o} = \frac{V_{s}}{R_{s}} ≅ i_{r}$ : Design a hill-climbing control in Fig. 7 to tune parameter Δt₃ so that the output shunt voltage V_s = i_oR_s to follow a given reference V_r via the feedback signal V_s;

CC or CV with slowly rising control: Let the output voltage or current reach the desired one at a time setting t_set shown in Fig. 9.

3. Methodology of digital PWM control with slowly rising time

The output port of the digital PWM controller is to produce four PWM square waves like Fig. 2. Then input to the power switching elements IGBTs. The following will describe the construction of the PWM square wave.

The Q_A square wave in Fig. 2 can be implemented by a counter and a comparator. Take an example to explain its design concept. In order to generate a 15KHz pulse of periodic wave, the counter with clock oscillation frequency 50 MHz counts up from 0 to 3334, repeatedly, and is compared with a constant 1607 to get a QA square wave. Mathematical express is shown as below: $If i < 1607 then$ $Q_{A} = 1; for i = 0 \sim 3334; periodic counter$ (6a) $Else QA = 0$ (6b)

where 3334 is the upper limit of the counter required to generate 15 kHz periodic pulse wave under 50 MHz clock oscillation frequency. This forms a high-low square wave with 0.48 duty cycle because that 1607 is about 0.48 times the 3334. The corresponding Simulink program is shown in Fig. 4a. We use the oscillation frequency of 50 MHz as a counter to make a PWM waveform with a period of 15KHZ = 1/15000 second. That is, the time up counting one is 1/50000000 seconds. So it is necessary to count up from 0 to 3334≈50MHZ/15KHZ to form a PWM waveform with 15KHZ frequency. The schematic diagram is shown in Fig. 4b.

Fig.4a

Q_A PWM program by Simulink.

Fig.4b

The PWM structure formulated by the comparator and counter.

Fig.4c

Simulation of Fig. 4a by Simulink tool.

Δt₁ gap time shown in Fig. 2, assuming 60 step counts. Q_B square wave in Fig. 2 can be mathematically expressed as follows: $\begin{matrix} If i > 1607 + 60 \\ then Qb 1 = 1; for i = 0 \sim 3334; periodic counter \end{matrix}$ (7) $Else Qb 1 = 0;$ (8) $\begin{matrix} If i < 3334 - 60 \\ then Qb 2 = 1; for i = 0 \sim 3334; periodic counter \end{matrix}$ (9) $Else Qb 2 = 0$ (10) $Q_{B} = AND (Qb 1, Qb 2) .$ (11)

From (7) to (11), we can design a corresponding Simulink program shown in Fig. 5. The remaining Q_C and Q_D waves’ programs are designed in Fig. 6, where delt _ t3 ≜ Δt₃ and delt _ t2 ≜ Δt₂ are same of the one in Fig. 2.

Fig. 5.

QB PWM program by Simulink.

Fig. 6.

Q_C and Q_D of PWM program by Simulink.

Design four PWM square waves by Simulink software shown in Figs. 4–6 to meet the clock pattern of Fig. 2 where Δt₃ is the simultaneously delay time of Q_C and Q_D PWMs. From Fig. 2, the range of Δt₃ is $0 < Δ t_{3} < 1607 .$ (12)

Controlling the delay time Δt₃ is equivalent to control the overlap Δt₄ of (Q_A, Q_D) and (Q_B, Q_C) two pairs of PWM waves, such that load output can approach to the reference input. Longer (Shorter) Δt₃ is, shorter (longer) the overlap Δt₄ is such that the DC load output V_o becomes lower (larger). Therefore, the closed loop control circuit of Fig. 1 can be re-written as system block Fig. 7. We mathematically express hill-climbing control in Fig. 7 as below: $Δ t_{3} ≜ u (k) ≜ 0 \sim 1067$ (13) $V_{err} = V_{o} - V_{r}$ (14) $u (k) = u (k - 1) + p$ (15)

$\begin{matrix} If 1 < V_{err} \\ then u (k) = u (k - 1) + p; for p = 1 \end{matrix}$ (16a) $\begin{matrix} If - 1 ⩽ V_{err} ⩽ 1 \\ then u (k) = u (k - 1) + p; for p = 0 \end{matrix}$ (16b) $\begin{matrix} If V_{err} < - 1 \\ then u (k) = u (k - 1) + p; for p = - 1 (16 c) \end{matrix}$ (16c)

Fig. 7.

Constant voltage control.

where p of climbing step here is chosen as positive one, negative one or zero to guide the controlled output to reach the desired target, V_o ≈ V_r.

In Fig. 1, if the voltage V_o is used as a feedback control signal, this control scheme is defined as a constant voltage control. On the other hand, since the voltage increasing or decreasing between the shunt resistance R_s is proportional to the magnitude of the current flowing through the shunt R_s according to Ohm’s Law. If using the terminal voltage V_s as feedback signal, it can be regarded as constant current control shown in Fig. 8 whose mathematical expression are: $V_{Ier} = V_{s} - V_{r}$ (17) $u (k) = u (k - 1) + p$ (18)

Fig. 8.

Constant current control.

$\begin{matrix} If 1 < V_{Ier} \\ then u (k) = u (k - 1) + p; for p = 1 (19 a) \end{matrix}$ (19a) $\begin{matrix} If - 1 < V_{Ier} < 1 \\ then u (k) = u (k - 1) + p; for p = 0 (19 b) \end{matrix}$ (19b) $\begin{matrix} If V_{Ier} < - 1 \\ then u (k) = u (k - 1) + p; for p = - 1 . (19 c) \end{matrix}$ (19c)

Longer the climbing step p in (15) and (18), the shorter rising time to load output is. That is, from Figs. 7 and 8, we know that the DC output V_o will quickly approach the desired one V_r for a suitable magnitude step p. But the electroplating industry needs that the DC output should gradually and linearly reach the desired one at a preset rising time t_set. In order to satisfy the electroplating factories’ demand of the slowly rising output of DC converter. This paper adds a linear saturation block behind the reference input signal whose schematic block is shown in Fig. 9. The linear saturation block is $V_{r 1} (t) = \frac{1}{t_{set}} t$ (20)

Fig. 9.

DC converter with slow rising control. (a) Original system output with fast response. (b) Gradually slow output response.

where t_set is a preset rising time shown in Fig. 9(b). The output response of the original closed-loop system circuit Fig. 9(a) quickly reach the desired one. Take use of Fig. 9(a)’s function, add linear saturator behind the reference input to obtain the gradually slow output of the DC converter shown in Fig. 9(b).

4. Experimental results of 7.2KW DC-DC converter with FPGA controller

In order to verify that the proposed control is feasible, the corresponding parameters of controlled full-bridge simplified circuit Fig. 1 are given below: input DC voltage V_in = 220 Volts, inductance L_o = 50uH, Capacitance C_o = 82000uF, shunt resistance R_s = 12/600 = 0.02 Ohm, turn ration of the center-tapped transformer is 26:1, all of the frequencies of Q_A ∼ Q_D PWM square periodic waves are 15KHz, A/D (Analog to Digital) sampling frequency is 2MHz, the maximum load current = 600A, maximum load voltage = 12 Volts, load resistance R_o = 0.02 Ohm, the time interval Δt₁ = Δt₂ = 1.2 * 10^-10 seconds of Fig. 2 are set.

The digital development board with Altera Cyclone IV FPGA chip is used in this paper. Experiment separately with the following items:

Constant voltage control: The load output voltage V_o can be controlled to follow a given reference voltage V_r which is set 500 (indicates 5.00 Volts). Experimental results are shown in Fig. 10.

Constant current control: The load current I_o is controlled to approach the reference value which is set 100 (indicates 100 Amperes). The experimental situation and measurement data are shown in Fig. 11.

Constant current control for slowly rising output: Reference input current 100 amps whose rising time are set at 7 seconds. That is, output current approaches 100 Amperes at 7 seconds. Its experimental measurement data are shown in Fig. 12.

Zero voltage switching (soft switching): In the constant current 100 ampere control, we measure power switching element IGBT’s terminal voltage whose waveform shown in right of Fig. 13, no jitter voltage phenomenon. We also present a hard-switching plot with jitter in left of Fig. 13 as a contrast.

Fig. 10.

Constant voltage control for 5 volts reference input.

Fig. 11.

Constant current control for 100 Amperes reference input.

Fig. 12.

constant current control with slowly rising 7 seconds for 100 amps reference input.

Fig. 13.

Comparison between hard and soft switching under Constant current control of 100 Amperes.

From above experimental illustration, it is sufficient to demonstrate that the proposed digital controller based on the FPGA chip is feasible to constant voltage/current control of DC converter. It also can control the output to attain desired one at a preset rising time. Furthermore, there is soft switching function to achieve the benefit of energy conservation.

5. Conclusions

In this paper, we successfully implement a digital control based on the FPGA chip to accomplish constant voltage/current with slowly rising control for a 7.2 KW full-bridge DC converter circuit. The soft switching is also achieved to reduce energy consumption. The proposed HDL code is not directly written in Verilog language, but with Matlab/Simulink verification and then transform the Matlab/Simulink program into the corresponding HDL code. Its advantage is simultaneously to complete and verify the desired HDL code. Comparing digital programming and traditional IC design, we know the advantage of digital programming is: (1) it is flexible and can be updated at any time by language program; (2) saving hardware space; and (3) the development cost is reduced. This is why the digital program is the mainstream of modern industrial control.

References

Lin ,

Wang ,

Rong and

Yu , The design of electric car DC/DC converter based on the phase-shifted full-bridge ZVS, Energy Procedia 88 (2016), 940–944.

C.-T.

Tsai ,

T.-C.

Liang ,

Y.-C.

Kuo and

Y.-C.

Luo , An improved forward converter with PFC and ZVS features for split-phase charger applications, Computers & Electrical Engineering 51 (2016), 291–303.

M.A.

Al-Saffar ,

E.H.

Ismail and

A.J.

Sabzali , Family of ZC-ZVS converters with wide voltage range for renewable energy systems, Original Research Article, Renewable Energy 56 (2013), 32–43.

Wang ,

Rong and

Li , Research on control strategy of the bidirectional full-bridge DC/DC converter used in electric vehicles, Energy Procedia 88 (2016), 964–969.

Genc and

Koc , Experimental verification of an improved soft-switching cascade boost converter, Electric Power Systems Research 149 (2017), 1–9.

Kowstubha ,

Krishnaveni and

Ramesh Reddy , Performance analysis of pulse analog control schemes for LLC resonant DC/DC converters suitable in portable applications, Journal of Electrical Systems and Information Technology 3 (2016), 454–470.

Zhifu ,

Yupu and

Yinan , Design of closed-loop control system for a bidirectional full bridge DC/DC converter, Applied Energy 194 (2017), 617–625.

Lin ,

Wang ,

Rong and

Yu , The design of electric car DC/DC converter based on the phase-shifted full-bridge ZVS control, Energy Procedia 88 (2016), 940–944.

Wang ,

Rong and

Li , Research on control strategy of the bidirectional full-bridge DC/DC converter used in electric vehicles, Energy Procedia 88 (2016), 964–969.

10.

V.F.

Pires ,

Foito and

J.F.

Silva , A single switch hybrid DC/DC converter with extended static gain for photovoltaic applications, Electric Power Systems Research 146 (2017), 228–235.

11.

Elangovan ,

Saravanakumar and

Nigam , Design and implementation of soft switched high gain current fed full bridge DC-DC converter for fuel cell applications, Energy Procedia 54 (2014), 246–259.

12.

Zhifu ,

Yupu and

Yinan , Design of closed-loop control system for a bidirectional full bridge DC/DC converter original research article, Applied Energy 194 (2017), 617–625.

13.

Piao ,

Qiao and

Teng , Digital control algorithm for two-stage DC-DC converters original research article, Energy Procedia 16(Part A) (2012), 265–271.

14.

Sadek ,

Sarjas ,

Chowdhury and

Svecko , FPGA-based optimal robust minimal-order controller structure of a DC-DC converter with Pareto front solution, Control Engineering Practice 55 (2016), 149–161.

15.

Sivavara Prasad ,

Y.P.

Obulesh and

Ch.S.

Babu , FPGA (Field Programmable Gate Array) controlled solar based zero voltage and zero current switching DC-DC converter for battery storage applications, Energy 106 (2016), 728–742.

16.

J.D.

Chryssis , High-frequency switching power supplies: Theory and design, New York: McGraw-Hill, c1989.

17.

M.-G.

Kim ,

G.-Y.

Park ,

D.-H.

Yoo and

G.-Y.

Jeong , High power full-bridge DC-DC converter using a center-tapped transformer and a full-wave type rectifier, International Journal of Control and Automation 7 (2014).

18.

Analysis and implementation of full-bridge converter with current doubler rectifier, IEE Proceedings - Electric Power Applications 152 (2005), 193–1202.