Simulation of voltage resistance testing for 12-bit low-power ADC chips

Abstract

With the popularity of portable electronic devices, the demand for 12-bit low-power analog-to-digital converter (ADC) chips continues to grow. Considering that these devices typically rely on battery power, high precision and stability are crucial. In order to improve the voltage resistance of ADC chips under high voltage, an innovative bootstrap sampling switch design is proposed, which utilizes the capacitance characteristics of NMOS and PMOS transistors to enhance the voltage resistance of the chip. At the same time, considering factors such as power fluctuations, time domain and voltage interleaving, a two-stage hybrid architecture based on successive approximation registers (SARs) and time to digital converters (TDCs) was studied and designed to optimize the balance between low power consumption and high voltage resistance performance. The results showed that the power consumption of the chip design was only 9.5 mW. The voltage compensation measures significantly reduced the error value from 7.01% to 1.97%, optimizing 5.04%. In summary, this design not only improves the accuracy and speed of ADC chips, but also successfully controls the exponential growth of power consumption, which has strong practical value. The proposed solution by the research institute has broad potential in multiple application fields, especially suitable for situations with high requirements for power consumption and stability, such as medical imaging and aerospace. This design provides new ideas and directions for the development of high-performance and low-power ADC chips in the future.

Keywords

low power consumption pressure resistance circuit simulation voltage stability ADC chip

Introduction

In today’s electronic systems, analog-to-digital converters (ADCs) play an indispensable role, especially in the fields of precision measurement and portable devices.¹ Among them, 12-bit low-power ADC chips are highly favored due to their excellent accuracy and energy-saving characteristics. This type of ADC chip is widely used in fields such as healthcare, environmental monitoring, portable instruments, and industrial control systems.² However, in practical applications, ADC chips face many challenges, especially the impact of voltage fluctuations on chip performance. Due to external factors such as power fluctuations, temperature changes, and signal interference, existing ADC designs often struggle to ensure stable performance in these unstable voltage environments, resulting in decreased accuracy and increased power consumption. In response to this issue, an innovative bootstrap sampling switch design has been proposed, aiming to significantly improve the voltage resistance performance of 12-bit low-power ADC chips under high voltage, while optimizing power consumption and accuracy. Therefore, evaluating the withstand voltage performance of ADC chips is crucial to ensure their reliability and stability under various working conditions. Voltage resistance refers to the maximum voltage that electronic components can safely withstand without damage.³ For low-power ADC chips, superior withstand voltage performance can not only improve product safety and reduce failure rates, but also extend product lifespan, especially in voltage unstable environments. With the development of technology, the sampling rate of 12-bit resolution ADC chips has been increased to 18 Gb/s.⁴ When the sampling phase is constant, the higher the single-phase sampling speed and accuracy, the higher the accuracy and speed of the time-domain and voltage interleaved ADC chip.⁵ But its power consumption will show exponential growth with the increase of sampling bits and speed. Therefore, in this context, research is dedicated to designing an ADC chip that combines low power consumption and high voltage resistance. To this end, an innovative ADC chip design based on a two-level hybrid architecture of successive approximation register (SAR) and time to digital converter (TDC) was proposed to enhance the performance stability of low-power ADC chips in unstable voltage environments. The contribution of the research lies in providing a high voltage resistance, low power consumption, and high-precision ADC chip design scheme for future portable electronic devices, especially suitable for applications with strict requirements for power consumption and stability.

The research content includes four parts. The second part is a review of the current research status of ADC chips and SAR-ADC chips both domestically and internationally. The third part is the design of a 12-bit low-power two-level hybrid architecture ADC chip circuit. The first section conducts research on the ADC chip architecture based on SAR-TDC, and the second section conducts low-power circuit design for a 12-bit resolution ADC chip. The fourth part is the simulation verification of a 12-bit low-power two-level hybrid architecture ADC chip circuit.

Related works

ADC chips can convert analog signals into digital form for electronic devices to process and analyze, so they have received widespread attention in many fields, and many researchers have conducted in-depth research on them. Researchers such as Pazhouhandeh M R proposed a 32 channel bidirectional CMOS neural interface to achieve efficient treatment of neurological diseases. Each channel of this design contains a neural ADC, and the effectiveness of this method was demonstrated through whole brain validation in rodents.⁶ To address the challenges of high-performance analog integrated circuit design in nanoscale CMOS technology, Gielen GGE et al. proposed a time coding based ADC method. This method used ADC technology of voltage controlled oscillators to achieve the functions of analog circuits in a highly digitized form. The results showed that this method was feasible in addressing the challenges of nanoscale CMOS technology.⁷ To minimize the power consumption and cost of ADC, Mulleti S and other scholars proposed a prototype design of modular computing hardware, which adopted modular folding technology to avoid signal clipping. In addition, to fold signals with higher frequencies than existing hardware, modular hardware operated before sampling. The results showed that this method effectively reduced the power consumption and cost of ADC.⁸

The SAR-ADC chip stands out among numerous ADC chips due to its advantages of low power consumption and medium to high precision, becoming a current research hotspot. To improve the efficiency and energy-saving performance of ADCs, Yi P’s research team proposed a compact noise shaping SAR-ADC based on error feedback structure. This method used a unit gain buffer and a ping-pong operation delay element to replace the traditional cascaded integrator feedforward structure for error feedback. The results showed that the design achieved a signal to noise ratio (SNR) and signal to noise distortion ratio (SNDR) of 79.3 dB at 16 times oversampling ratio.⁹ Miki T and other scholars proposed a method called “random interrupt jitter technique” to enhance the defense ability of SAR-ADC against bypass attacks. This technology reduced the correlation between the analog input and the reference charge flow by introducing a significant jitter in the analog input, which was equivalent to a quarter of the full scale of the ADC. The results showed that compared to traditional reference charge bypass attacks on SCA, this innovative tamper proof ADC could reduce information leakage to 0.8 bits.¹⁰ Tang X et al. proposed a second-order noise shaping technique with a closed-loop dynamic amplifier to enhance the energy efficiency of SAR-ADC in the face of process, voltage, and temperature changes. This technology adopted a closed-loop structure and dynamic operation, embedding a closed-loop dynamic amplifier into a loop filter designed for second-order noise shaping SAR. The results showed that this method effectively improved the energy efficiency of SAR-ADC.¹¹

In the current ADC design, especially in the demand for low power consumption and high voltage resistance, a large amount of research work has made progress in this field. In order to improve the performance of ADCs in different application scenarios, many studies have focused on addressing the stability issues of traditional ADCs in high voltage fluctuation environments and the challenges of low-power design. For example, Jiang Z et al. proposed a high linearity broadband front-end design with integrated high-voltage assistance, aimed at addressing the issues of insufficient bandwidth and stability in existing ADC front-end. This design utilizes on-chip high-voltage generation technology to achieve high rotational current injection, significantly improving the performance of high-speed ADCs.¹² However, this design mainly focuses on improving bandwidth and linearity, with less emphasis on balancing power control and high voltage resistance. Further optimization is still needed in terms of power stability and power consumption. Huang W’s research team has proposed a design strategy based on human effects and multiple voltage domains, aimed at improving the performance of high-voltage ADCs in radiation environments. This method combines circuit and layout strategies, enhances the radiation tolerance of ADC through the combination of multi voltage domain characteristics, human body effects, and total ionizing dose (TID) effects, especially improving its TID tolerance in radiation environments.¹³ Nguyen V and other scholars proposed an ultra-low voltage ADC design to address the frequency digitization accuracy issue of ultra-low voltage frequency to digital converters (FDCs) in voltage controlled oscillators (VCOs). This method effectively solves the variability problem of phase sampling circuits and improves the accuracy and stability of ADCs at low voltages.¹⁴ The literature review summary is shown in Table 1.

Table 1.

Summary of literature review.

Research	Achievements	Shortcomings
Pazhouhandeh M R et al.⁶	Neural ADC verified to be effective through in vivo whole-brain experiments	Focused on treatment of neurological disorders; insufficient discussion on power and accuracy optimization
Gielen G G E et al.⁷	Proven feasible in nanoscale CMOS technology	Focused only on digital implementation; potential trade-offs between power consumption and accuracy
Mulleti S et al.⁸	Effectively reduced ADC power consumption and cost	Primarily focused on power and cost; did not address accuracy improvement or reliability in complex applications
Yi P et al.⁹	Achieved 79.3 dB SNR and SNDR under 16× oversampling ratio	Focused on low power and high precision, but may lack stability in extreme environments
Miki T et al.¹⁰	Successfully reduced information leakage to 0.8 bits	The method may introduce significant jitter in high-frequency applications, limiting its applicability
Tang X et al.¹¹	Improved energy efficiency of SAR-ADC.	Focused on energy efficiency; may overlook power supply stability and performance under low-voltage conditions
Jiang Z et al.¹²	Enhanced high-speed ADC performance by solving bandwidth and stability issues	Less attention to power consumption and high-voltage tolerance; further optimization needed in these areas
Huang W et al.¹³	Improved ADC radiation tolerance, particularly under TID environments	Mainly targeted at radiation environments; lacks focus on low power and broader application performance
Nguyen V et al.¹⁴	Improved accuracy and stability of ADC under ultra-low voltage	May involve trade-offs between power and accuracy in high-frequency operations

In summary, many existing ADC designs, such as the noise shaping SAR-ADC proposed by Yi P and the second-order noise shaping design proposed by Tang X, have not fully focused on stability and high reliability at extremely low voltages while pursuing high energy efficiency and accuracy. Moreover, under high-frequency operation, these designs may face additional power consumption and accuracy losses. In addition, although Nguyen V et al.'s ultra-low voltage FDC design solves the variability problem under low voltage, power consumption and stability issues still exist under high-frequency operation. In response to the above limitations, an innovative ADC chip design scheme with high voltage resistance, low power consumption, and high precision has been developed. Leverage the capacitance properties of NMOS and PMOS transistors to enhance the voltage tolerance of the chip, thereby offering device manufacturers more stable and reliable products.

Circuit design of a two-level hybrid architecture ADC chip with 12-bit low power consumption

This chapter explores the basic architecture of SAR-ADC chips and analyzes the quantization process of ADC chips based on SAR-TDC, revealing their innovative applications in time coding and digital conversion. Research on ADC chips based on SAR-TDC is expected to provide new basis for mixed signal integrated circuit design and a new perspective for efficient ADC implementation.

ADC chip based on SAR-TDC

SAR is a technique used for ADC, which allows for the conversion of analog signals into digital signals through a stepwise approximation method.¹⁵ SAR-ADC is an efficient, precise, and widely used converter for low-power and medium speed applications. Due to its stepwise approximation method, SAR-ADC does not require continuous comparison operations, which often leads to lower power consumption. Compared with other types of ADCs, the design of SAR-ADC is relatively simple because it does not require complex clock management or high-speed operational amplifiers. The basic architecture of the SAR-ADC chip is shown in Figure 1.

Figure 1.

The basic architecture of SAR-ADC chip.

As shown in Figure 1, SAR-ADC mainly consists of sample and hold (S/H) circuit, digital to analog converter (DAC), comparator, SAR, and TDC. SAR is responsible for generating digital outputs, while DAC converts these digital values into analog signals for comparison. The comparator determines the size relationship between the input signal and the DAC output, while the timing controller ensures that the data conversion process proceeds in an orderly manner. The evaluation indicators for ADC performance include static and dynamic characteristics. The static characteristics focus on the performance of the device in steady-state, while the dynamic characteristics describe the performance when the input signal changes dynamically.¹⁶ Resolution, bias error, signal-to-noise ratio, and sampling rate are key indicators for evaluating ADC performance.¹⁷ The resolution of ADC refers to its ability to recognize and convert the minimum amount of variation in the input signal.¹⁸ In the digital field, resolution is usually expressed as the number of bits that ADC can convert. In the field of simulation, resolution refers to the minimum input voltage change that the ADC can detect.¹⁹ The mathematical expression for resolution is shown in equation (1).

R = \frac{V}{2^{N}}

(1)

In equation (1), $R$ represents resolution, $V$ represents voltage, and $N$ represents the number of bits that ADC can convert.²⁰ The resolution of a comparator refers to the minimum voltage difference it can distinguish, which can be calculated by dividing the minimum output change it can detect by its gain. Therefore, the resolution formula of a comparator is shown in equation (2).

R_{C} = \frac{(V_{O H} - V_{O L})}{A_{v}}

(2)

In equation (2), $R_{c}$ represents the resolution of the comparator, $V_{O H}$ and $V_{O L}$ represent the high and low levels of the comparator output, respectively, and $A_{v}$ represents the comparator gain. Differential nonlinearity refers to the analog input voltage difference between any two consecutive digital output codes in an ideal ADC. The mathematical expression for differential nonlinearity is shown in equation (3).

D N L = \frac{x_{i} - x_{i - l}}{l} - 1

(3)

In equation (3), $D N L$ represents differential nonlinearity, $x_{i}$ represents the $i$ -th digital code, and $l$ represents the conversion length between digital codes. Integral nonlinearity refers to the maximum deviation between the actual conversion characteristic curve and the ideal straight line. The mathematical expression for integral nonlinearity is shown in equation (4).

I N L = \sum_{i = l}^{n} D N L_{i}

(4)

In equation (4), $I N L$ represents integral nonlinearity, and $n$ represents the number of digital codes. The mathematical expression for signal-to-noise ratio is shown in equation (5).

S N R = 10 \log \frac{W_{i n}}{W_{n o}}

(5)

In equation (5), $S N R$ represents signal-to-noise ratio in dB, while $W_{i n}$ and $W_{n o}$ represent signal energy and noise energy, respectively. As the demand for power supply voltage decreases, traditional pipeline ADC chips face a series of challenges in low voltage environments, such as increased difficulty in simulation design and reduced noise tolerance. In contrast, ADC based on time to digital converter (TDC) is gradually gaining attention due to its advantages of high noise tolerance and low power consumption. However, the linearity and resolution of TDC-ADC are still limited by the performance of voltage time converter (VTC) and TDC.²¹ To address these issues, research is being conducted to combine SAR with TDC and design a two-level hybrid architecture ADC chip solution. This hybrid architecture utilizes SAR for coarse quantization, while TDC is responsible for fine quantization and further improves accuracy by introducing redundant bits. The quantization process of the ADC chip based on SAR-TDC is shown in Figure 2.

Figure 2.

The quantization process of ADC chip based on SAR-TDC.

As shown in Figure 2, the quantization process in the SAR-TDC hybrid ADC chip is performed as a reference voltage, with the quantization range of SAR-ADC ranging from 0 to $V_{r e f}$ . The quantization process can be imagined as a series of gradual approximation steps aimed at aligning the input voltage with the common mode level, represented by the red line in the graph. The residual voltage generated by each step of approximation, that is, the difference between input voltage and common mode level, will fall within 1LSB of SAR-ADC. This residual voltage is then mapped in the time domain, corresponding to a time delay from $T_{0}$ to $T_{r e f}$ . In time-domain TDC, the position of this mapping is represented by the purple line in the time domain. Through this mapping, the rough quantization results of SAR-ADC can be refined, resulting in improved conversion accuracy.

Low-power circuit design of ADC based on 12-bit resolution SAR-TDC

When exploring ADC chips based on SAR-TDC architecture in depth, a signal acquisition and conversion mechanism combining the high-speed operation characteristics of TDC with the low energy consumption advantages of SAR was proposed. Aiming at the dual requirements of low power consumption and high voltage resistance, an ADC circuit based on 12-bit resolution SAR-TDC was studied and designed. In the circuit design process, optimization strategies such as dynamic residual amplification and bootstrap sampling switches were adopted to reduce power consumption while improving conversion rate and dynamic performance. The hybrid architecture based on SAR-TDC adopts a two-stage design. In the first stage, the SAR module is used to roughly approximate the input signal, while in the second stage, the TDC module is used to accurately measure the approximated signal. The innovation of this design architecture lies in the use of a bootstrap sampling switch design based on the capacitance characteristics of NMOS and PMOS transistors to enhance the stability of the chip in high voltage environments. This design effectively reduces errors caused by voltage fluctuations and ensures higher accuracy during the sampling process. In addition, the study also utilizes dynamic residual amplification technology to dynamically amplify signal residuals, in order to further improve the linearity and signal-to-noise ratio of the system, thereby optimizing performance under low power consumption. The low-power ADC circuit based on 12-bit resolution SAR-TDC is shown in Figure 3.

Figure 3.

Low-power ADC circuit based on 12-bit resolution SAR-TDC.

As shown in Figure 3, in the low-power circuit design of SAR-TDC hybrid ADC based on 12-bit resolution, an 8-bit resolution SAR-ADC architecture and a 4.5-bit resolution TDC-ADC architecture are integrated, with a 0.5-bit resolution used as redundant bits to improve the robustness of the system. This design also integrates a data fusion module and a residual transfer module to optimize data processing and accuracy during the conversion process. Among them, the SAR-ADC part includes a comparator, sampling switch, logic control circuit, and a binary capacitor array, responsible for preliminary ADC. In the integration part of TDC-ADC, the system adopts VTC, edge detector, TDC, and a dynamic residual amplifier to achieve finer conversion accuracy. The design of the dynamic residual amplifier considers the compensation mechanism for power supply fluctuations and temperature drift, and is manufactured using a 40 nm complementary metal oxide semiconductor process. In terms of power supply design, SAR-ADC and dynamic residual amplifiers use a 1.1 V power supply, while other components use a 0.8 V low voltage power supply. This layered power strategy helps to reduce overall power consumption, ensuring system energy efficiency and performance.²² The binary capacitor array of SAR-ADC is shown in Figure 4.

Figure 4.

Binary capacitive array of SAR-ADC.

As shown in Figure 4, the SAR-ADC section uses a binary capacitor array consisting of 8 capacitor units labeled C1 to C8. Their capacitance values are set to (1, 2, 4, 8, 16, 32, 64, 128) times the reference capacitance C, forming an accurate binary weighted array for precise charge allocation and adjustment of the input signal during ADC. In terms of differential input, $V_{i p}$ and $V_{i n}$ represent positive differential input voltage and negative differential input voltage, respectively, and together they define the differential mode level of the input signal. $C_{l k s}$ is a sampling clock used to synchronize the charging and discharging operations of the capacitor array, ensuring that the conversion process is synchronized with the system clock. $V_{c m}$ is the common mode voltage, which is the midpoint voltage of the capacitor array, representing the average voltage level of the differential signal. After quantifying the binary capacitor array of SAR-ADC, the residual voltage can be calculated as shown in equation (6).

V_{r e s} = (V_{i n} - V_{i p}) - (\sum_{i = 0}^{k - 1} V_{r e f} \times \frac{2^{i} C}{2^{n} C} \times B_{i})

(6)

In equation (6), $V_{r e s}$ represents residual voltage, $k$ represents the number of bits in SAR-ADC, and $B_{i}$ represents the sign bit corresponding to the $i$ digit code. If SAR-ADC uses the top board sampling strategy, there will be a parasitic capacitor at the input of the comparator directly connected to the capacitor array of the DAC. In this case, the residual voltage may shift due to this parasitic capacitance, and the mathematical expression for the residual voltage that generates the offset is shown in equation (7).

V_{r e s}^{'} = (V_{i n} - V_{i p}) - (\sum_{i = 0}^{k - 1} V_{r e f} \times \frac{2^{i} C}{2^{n} C + C_{P}} \times B_{i})

(7)

In equation (7), $V_{r e s}^{'}$ represents the residual voltage that generates offset, and $C_{p}$ represents parasitic capacitance. This formula illustrates that in SAR based ADC design, parasitic capacitance can cause voltage offset during sampling, thereby affecting the accuracy of the signal. Therefore, by optimizing the parasitic capacitance and sampling switch configuration in circuit design, this voltage offset can be reduced, thereby improving the accuracy of ADC. The transfer function of the sampling switch is shown in equation (8).

F (j w) = \frac{1}{1 + j w R_{s} C_{D A C}}

(8)

In equation (8), $F$ represents the transfer function, $j$ and $w$ represent complex units and angular frequency, $R_{s}$ represents switching resistance, and $C_{D A C}$ represents the capacitor array of DAC. This formula reveals the transmission characteristics of sampling switches, especially at high frequencies, where switch resistors and capacitor arrays have a significant impact on signal transmission. Therefore, in circuit design, optimizing the transfer function is the key to improving conversion rate and dynamic performance. The expression for the switch resistance is shown in equation (9).

R_{s} = \frac{1}{ν C_{o x} (V_{g s} - V_{t h}) \times \frac{W}{L}}

(9)

In equation (9), $ν$ represents the charge rate, $V_{g s}$ and $V_{t h}$ represent the gate source voltage and threshold voltage, $C_{o x}$ represents the capacitance of the gate oxide layer, $W$ and $L$ represent the gate width and gate length of the transistor, respectively. This formula indicates that the size of the switch resistor directly affects the conversion accuracy and power consumption of the ADC. Therefore, in the design, the switch resistance can be reduced by selecting appropriate materials and optimizing the switch structure, thereby improving overall performance. The output voltage of the sampling switch is shown in equation (10).

V_{o u t} = V_{i n} (1 - e^{- \frac{t}{R_{s} C_{D A C}}})

(10)

In equation (10), $V_{o u t}$ and $V_{i n}$ represent the output voltage and input voltage, respectively, $e$ represents the base of the natural logarithm, and $t$ represents time. The error voltage is shown in equation (11).

Δ V = V_{i n} \times e^{- \frac{t}{R_{s} C_{D A C}}}

(11)

In equation (11), $Δ V$ represents the error generated between the input voltage and the output voltage. The time required to reach the predetermined error voltage is shown in equation (12).

T_{r e s} = - R C_{D A C} \times \ln \frac{Δ V}{V_{i n}}

(12)

In equation (12), $T_{r e s}$ represents the time to reach the predetermined error voltage. The output noise power is shown in equation (13).

P_{o u t} = \frac{ε T}{C_{D A C}}

(13)

In equation (13), $P_{o u t}$ represents the output noise power, and $ε$ represents the Boltzmann constant. The quantization error power is shown in equation (14).

P_{q u a} = {(\frac{V_{r e f}}{2^{12} \sqrt{12}})}^{2}

(14)

In equation (14), $P_{q u a}$ represents the quantization error power. As a 12-bit resolution SAR-TDC is designed, the accuracy of SAR-TDC is 12. To ensure system performance, it is necessary to output noise power that is less than one-third of the quantization error power. The ratio of output noise power to quantization error power is shown in equation (15).

\frac{ε T}{C_{D A C}} < \frac{1}{3} \times {(\frac{V_{r e f}}{2^{12} \sqrt{12}})}^{2}

(15)

MOSFETs, especially NMOS transistors, are widely used as sampling switches due to their fast switching performance and small size. These switches utilize the conduction capability of MOSFETs, allowing the circuit to accurately sample analog signals based on the frequency of the clock signal. However, the conduction resistance of MOSFETs is not fixed and will change with time, especially when the value of $V_{g s}$ approaches $V_{t h}$ , its nonlinear performance is particularly evident. This means that during the sampling process, if the input signal amplitude is large, changes in the switch resistance may cause signal distortion. To reduce the impact of nonlinearity on conversion accuracy, the parasitic diode junction capacitance characteristics of NMOS and PMOS transistors are studied to compensate for the nonlinearity of NMOS switches, and a bootstrap sampling switch was designed. In this design, a bootstrap sampling switch based on the capacitance characteristics of NMOS and PMOS transistors is used to overcome the nonlinear problem of traditional MOS switches at high voltages and optimize the accuracy of the sampling process. When the clock signal $C L K$ is at a high level, the capacitor C will be charged to $V_{d d} + V_{i n}$ first, and then through a bootstrap process, the voltage of the capacitor will be further increased to $2 V_{d d} + V_{i n}$ to ensure that the gate voltage of the NMOS transistor is higher than the threshold, thereby effectively reducing the nonlinear effect of switch resistance. Due to the increased voltage of capacitor C, the voltage difference between PMOS and NMOS transistors is appropriately compensated, further reducing the impact of voltage changes on switch performance and enhancing the accuracy and stability of sampling. The circuit design of the bootstrap sampling switch is shown in Figure 5.

Figure 5.

Circuit design of bootstrap sampling switch.

As shown in Figure 5, in the circuit design of the bootstrap sampling switch, $C L K$ and $C L K N$ represent the clock signal and reverse signal. $M_{(1, 2, . . . ., 10)}$ refers to the transistor in the circuit. $C_{u p}$ and $V_{d d}$ represent the rising capacitor and positive power supply voltage, respectively. In this design, in the circuit design of the bootstrap sampling switch, when $C L K$ is at a high level, the voltage of the $C_{u p}$ upper board is first raised to $V_{d d} + V_{i n}$ , and then further raised to $2 V_{d d} + V_{i n}$ . This voltage boosting strategy ensures that the gate voltage of the transistor is always higher than its source voltage, thereby ensuring full conduction of the transistor. This not only reduces the variation of transistor switching resistance, but also significantly enhances its conductivity performance. The switch resistance is maintained at a low and constant level, significantly reducing the impact of voltage crossing on the sampling switch. In addition, the bootstrap circuit design further optimizes the equivalent resistance $R_{s}$ of the $M_{10}$ transistor, thereby improving the response speed of the sampling switch. Due to the decrease in switch resistance and rapid charge transfer, the sampling process can be completed quickly. This not only improves the speed of the sampling switch, but also enhances its overall performance.

In order to improve the stability and reliability of ADC chips in practical applications, a detailed design of voltage compensation and temperature compensation mechanisms was studied, and optimization was carried out based on the working principle of bootstrap sampling switches. In addition, in the implementation of compensation algorithms, a new compensation algorithm framework was proposed by combining error feedback structures with temperature and voltage compensation models. This algorithm utilizes polynomial fitting method to model the voltage and temperature changes under different working environments, ensuring the effectiveness and adaptability of the compensation mechanism. The voltage compensation model is shown in equation (16).

{V_{o u t}}^{'} (t) = V_{i n} (t) + α \cdot Δ V (t)

(16)

In equation (16), ${V_{o u t}}^{'} (t)$ represents the output voltage after voltage compensation, $Δ V (t)$ represents the voltage error, and $α$ represents the compensation coefficient. The temperature compensation model is shown in equation (17).

V_{o u t}^{″} (t) = V_{i n} (T) \cdot (1 + β \cdot Δ T)

(17)

In equation (17), $V_{o u t}^{″} (t)$ represents the output voltage after temperature compensation, $T$ represents the current temperature, $Δ T$ represents the temperature error, and $β$ represents the temperature compensation coefficient.

Simulation verification of a 12-bit low-power two-level hybrid architecture ADC chip circuit

This chapter first set up a simulation experimental environment, and then simulated the circuit of the ADC chip to further verify its resistance voltage performance. Through simulation experiments, the performance of the ADC chip was comprehensively evaluated, providing reliable basis for subsequent practical applications.

Experimental environment construction

To verify the performance of a 12-bit low-power two-level hybrid architecture ADC chip circuit, simulation tests were conducted using SPICE’s circuit simulation platform. The hardware environment of the testing system mainly consists of the following parts: signal source, power supply, ADC chip testing system hardware platform, and computer. The temperature range used in the simulation is −40° C to 125° C, which covers the common operating temperatures in most application scenarios. During the simulation process, the power supply voltage range was set to 1.0 V–1.8 V to ensure the stability of the ADC under low and high voltage fluctuations. In addition, the simulation was conducted on the SPICE platform, using multiple components including signal sources, power supplies, ADC testing platforms, and computer systems. The specific simulation experiment environment configuration is shown in Table 2.

Table 2.

Specific simulation experiment environment configuration.

Device	Configuration
Signal source	Frequency is 722.89 kHz, amplitude is 1V sine wave
Power supply	12V
ADC chip testing system hardware platform	Virtex
Software platform	MATLAB
Computing system	Ubuntu16.04.7LTS
FMC interface	Analog devices

ADC chip circuit simulation results

The study conducted simulation tests on ADC chips using the SPICE simulation platform, and the simulation results of the ADC chips are shown in Figure 6. SNR reflects the energy ratio between the input signal and noise, and a higher SNR indicates that the analog signal is less affected by noise during the conversion process. SDR measures how much original signal components are retained in the output signal while suppressing how much nonlinear distortion is present. A higher SDR means that the ADC performs well in maintaining signal fidelity. THD represents the intensity of harmonic interference caused by nonlinear components during ADC conversion, with higher values indicating a more linear system and smaller harmonics. SNDR is a comprehensive indicator of SNR and SDR, which represents the overall cleanliness of the system and is suitable for measuring the overall system quality of ADC. ENOB measures the true resolution of ADC in practical operation, and the closer it is to the ideal 12-bit resolution, the closer the design is to the theoretical limit. As can be seen from Figure 6, the SNR reached 65.1 dB, indicating that there was only a small amount of noise in the signal, and the signal to distortion ratio (SDR) was 74.4 dB, indicating a high purity and low distortion of the signal. SNDR and total harmonic distortion (THD) were 64.9 dB and 78.3 dB, respectively, further emphasizing signal quality. The effective number of bits (ENOB) was 10.19 bits, indicating a high quantization accuracy of ADC. Therefore, all indicators of the ADC chip met the reading requirements of the chip.

Figure 6.

ADC chip simulation results.

To further verify the accuracy of the ADC chip’s digital conversion output, the study connected it to two inverters and conducted transient simulation analysis. In the simulation test, the sampling frequency was set to 50 MS/s and the transient simulation time was 10 ms. The transient simulation diagram of the ADC chip is shown in Figure 7. From Figure 7, the transient simulation output of the ADC chip presented a sinusoidal signal waveform. This result indicated that the ADC chip successfully completed digital conversion output and its functional performance was accurate and error free.

Figure 7.

Transient simulation diagram of ADC chip.

Simulation of voltage resistance performance of ADC chips

To verify the reliability and stability of ADC chips under various working conditions, a series of simulation tests were conducted to evaluate the gain performance of dynamic residual amplifiers under different temperature and power supply voltage conditions after implementing power fluctuation and temperature drift compensation mechanisms. The gain of the ADC chip after compensation under different working conditions is shown in Figure 8. From Figure 8(a), at a power supply voltage of 1.06 V, the chip achieved a maximum gain of 10.18 dB, while at 1.20 V, the gain slightly decreased, achieving a minimum gain of 9.95 dB. This change indicated that although the power supply voltage fluctuated, the compensation mechanism successfully limited the range of gain variation, ensuring the coherence and consistency of the chip output. From Figure 8(b), the ADC chip achieved a maximum gain of 10.20 dB at extreme low temperatures of −40°C, while the gain slightly decreased to 10.04 dB when the temperature increased to −10°C. Under different temperature conditions, the fluctuation of gain was controlled within a small range, demonstrating the excellent temperature adaptability and stable gain performance of ADC chips. In summary, with compensation mechanism, ADC chips could maintain the stability and reliability of their gain performance in the face of challenges such as power supply voltage fluctuations and temperature drift. In addition, the compensated gain stability ensures that the ADC can maintain consistent voltage conversion characteristics even under power supply fluctuations and temperature changes. Especially in outdoor or high-temperature industrial environments, this robustness is crucial for the long-term operation of the system.

Figure 8.

Gain of ADC chip after compensation under different working conditions. (a) Gain of ADC chip after compensation under different power supply voltages and (b) gain before and after compensation at different temperatures.

To further verify the voltage resistance of the ADC chip, a simulation test was conducted to compare the error values of the ADC chip before and after compensation, as shown in Figure 9. From Figure 9(a), in terms of voltage tolerance, the compensation measures greatly stabilized the error value, resulting in a significant decrease in error value from 7.01% before compensation to 1.97% at the application point of 1.06 V, an improvement of 5.04%. From Figure 9(b), under extreme temperature conditions as low as −40°C, the maximum error value after compensation was 2.02%, while without compensation, the error value was as high as 21.98%, a decrease of nearly 20%. Overall, the compensated ADC chip exhibited excellent performance in terms of voltage resistance and temperature adaptability.

Figure 9.

Comparison of error values before and after ADC chip compensation. (a) Error values before and after compensation under different power supply voltages and (b) error values before and after compensation for different temperatures.

For application devices such as medical monitoring equipment, industrial sensors, and high-speed communication systems that require high precision as their core, reducing errors will directly affect the accuracy of signal sampling. For example, in the field of automotive electronics, high-precision ADC chips are required for data acquisition of various sensors inside cars to ensure the accuracy of safety systems for drivers and passengers. ADC chips with low error and high stability can provide real-time and accurate environmental monitoring data, thereby improving automotive safety.

Errors can usually be divided into two types: systematic errors and random errors. Random errors are caused by uncertain factors and manifest as unpredictable fluctuations, while systematic errors usually have strong regularity. Therefore, sensitivity analysis has become an important tool for further understanding the variation of errors under different conditions. According to the simulation results under different temperature and voltage fluctuation conditions, the variation of system error shows a relatively obvious pattern. For example, in the extreme environment shown in Figure 9(b), after compensation, it decreased to 2.02%, proving that compensation measures can significantly reduce system errors caused by temperature. However, as voltage or temperature conditions further limit, random errors will also increase, especially in extreme environments where the response time and timing control of the chip may lead to an increase in small errors. Therefore, future research needs to conduct error sensitivity analysis within a wider range of temperature and voltage fluctuations to evaluate the interaction between system errors and random errors under different operating conditions, further improving the stability and reliability of chips in various extreme environments.

To verify the effectiveness of the strategy of compensating for the nonlinear behavior of NMOS switches using the inherent diode junction capacitance characteristics of PMOS transistors, a simulation comparative analysis was conducted on the ADC chips before and after improvement, as shown in Figure 10. From Figure 10, when the time reached 2.61 ns, the voltage response of the improved chip increased to 0.8 V, while under the same conditions, the pre improved chip did not reach the same voltage until 2.65 ns. This result indicated that the application of PMOS transistors effectively accelerated the response time of ADC chips, thus it can be seen that this compensation method helps to improve the overall conversion rate.

Figure 10.

Simulation diagram of ADC chip before and after PMOS transistor improvement.

To verify the superiority of the 12-bit low-power SAR-TDC two-level hybrid architecture ADC chip, it was compared with several common ADC designs. These designs included SAR-ADC based on dynamic amplifiers, high-speed low-power pipeline SAR-ADC, and SAR-ADC for space applications.²³ The performance parameters of different ADC chip designs are compared in Table 3. From Table 3, the sampling rate of the studied chip was as high as 200 MS/s, far exceeding the other three designs. This meant that it could collect data at a very high speed, meeting the needs of high-speed data collection. Secondly, in terms of power consumption, it was only 9.5 mW, which was the lowest among all designs. Compared with the other three designs, the power consumption of this chip was reduced by 7.05%, 16.84%, and 5.26%, respectively. In summary, the 12-bit low-power SAR-TDC two-level hybrid architecture ADC chip not only had high sampling rate, but also extremely low power consumption, which had significant advantages compared to other designs.

Table 3.

Comparison of performance parameters for different ADC chip designs.

Performance parameter	SAR-ADC based on dynamic amplifier	High-speed low-power pipeline SAR-ADC	Space-oriented SAR-ADC	12-bit low-power SAR-TDC two-level hybrid architecture ADC
Accuracy/bit	12	12	12	12
Supply voltage/V	0.9	1.8	1.8	3.3
Sampling rate (MS/s)	625	50	10	200
ENOB/bit	10.65	11.16	10.8	10.19
SDR/dB	76.5	76.3	78.6	74.4
Power consumption/mW	10.17	11.1	10	9.5

Low-power design has a significant impact on portable electronic devices. Low power consumption means an extension of battery life, which can support devices to operate stably for a long time without frequent charging. This is very important for improving user experience and device convenience. For example, in smart homes, the low-power characteristics of this chip are very suitable for low-power devices such as temperature and humidity sensors, smoke alarms, etc., enabling these devices to operate stably for a long time and reducing dependence on batteries.

To further validate the advantages of this design, a comparative analysis was conducted with other low-power ADC chips. The selected comparative designs included Texas Instruments’ (TI) ADS7041, Analog Devices’ AD7980, and Maxim Integrated’s MAX11108. These models are typical representatives of low-power applications in their respective product lines. A performance comparison was conducted on different low-power ADC chip designs, as shown in Table 4. From the table, it can be seen that the other three low-power chip designs have resolutions between 12 or 16 bits, but their sampling rates are only 1 MS/s. The ADC chip designed in this study has the highest sampling rate of 200 MS/s, which can meet the requirements of high-speed data acquisition. Although ADS7041 and MAX11108 have lower power consumption, their voltage resistance is only 2.5 V. In contrast, AD7980 has a voltage resistance of 3.3 V, but its power consumption is higher, reaching 10.5 mW, making it more suitable for high-resolution and precision measurement applications. In summary, the low-power design studied fully utilizes the advantages of high sampling rate and low power consumption, and has strong environmental adaptability, especially in maintaining stability under unstable voltage conditions.

Table 4.

Performance comparison of different low power ADC chip designs.

Chip design	Resolution	Sampling rate (MS/s)	Power consumption/mW	Pressure resistance/V
12-Bit low-power SAR-TDC two-stage hybrid architecture ADC	12-bit	200	9.5	3.3
ADS7041	12-bit	1	3.6	2.5
AD7980	16-bit	1	10.5	3.3
MAX11108	16-bit	1	5.5	2.5

Conclusion

In modern electronic systems, ADC, as a key component, is crucial for applications with high speed and low power consumption performance. To achieve a balance between fast and accurate data conversion and system power consumption, a high-performance 12-bit low-power ADC chip design was studied. The results showed that the SNR and SDR of the chip were 65.1 dB and 74.4 dB, respectively, indicating that the noise content in the signal was extremely low, the signal purity was high, and the distortion was small. Meanwhile, the SNDR and THD of the chip reached 64.9 dB and 78.3 dB, respectively, with an ENOB of 10.19 bits, further demonstrating its high quantization accuracy. In addition, the chip exhibited high gain stability when adjusting the power supply voltage from 1.06 V to 1.20 V. Its maximum gain was 10.18 dB and the minimum gain was 9.95 dB. Even within the extreme temperature range of −40°C to −10°C, the change in gain was only 0.16 dB, demonstrating good temperature stability. The voltage compensation measures significantly improved the performance of the chip at 1.06 V voltage. Through compensation, the error value was significantly reduced from 7.01% to 1.97%, optimizing 5.04%. Under extreme low temperature conditions of −40°C, the maximum error value after compensation was 2.02%, which was significantly improved compared to the uncompensated 21.98%. In summary, the simulation study of voltage resistance testing for 12-bit low-power ADC chips effectively reduced power consumption and enhanced voltage resistance.

However, there is still room for further improvement in research. Future work can be carried out in the following directions: firstly, further optimizing the data exchange mechanism between SAR and TDC modules to improve overall conversion accuracy; the second is to verify its robustness within a wider range of temperature and voltage fluctuations to meet the requirements of more complex application environments; the third is to explore circuit design based on new materials or heterogeneous integrated structures, in order to further break through the limitations of traditional CMOS processes in terms of power consumption and speed. This ADC chip has broad application prospects in fields such as medical imaging, wearable devices, and spacecraft navigation that require both high resolution and low power consumption. Future research can also focus on customized design for different application scenarios, in order to achieve the optimal match between performance and cost.

Although the current sampling rate is significantly better than traditional designs, there may still be a sampling rate bottleneck of 200 MS/s for some ultra-high speed signal processing scenarios. Therefore, future research can enhance the sampling capability of the entire system by improving the time resolution and parallel structure of the TDC module. Meanwhile, multi-phase parallel sampling or time interleaving (TI-ADC) technology can also be introduced to break through the single channel sampling rate limitation while maintaining low power consumption. In addition, future research can explore the possibility of combining SAR-TDC architecture with emerging technologies such as machine learning and artificial intelligence, such as introducing intelligent controllers to achieve adaptive quantization decision-making, or using neural networks for online correction of TDC delay errors.

However, the study did not discuss the performance of chips in more extreme working environments, so the research results are not yet comprehensive. For example, a decrease in the threshold voltage of MOS transistors at high temperatures may cause comparator mismatch or a decrease in sampling accuracy. Exceeding the upper limit of the rated voltage of the device may cause reliability degradation or device breakdown, as well as increased clock delay and analog signal response time under extremely low temperature conditions, which may affect sampling accuracy and timing control. Therefore, future research should consider using methods such as temperature accelerated aging testing and voltage transient impact simulation to further broaden the scope of verification and enhance the robustness and versatility of the design in extreme application environments.

Footnotes

ORCID iD

Yan Liang

Funding

The authors received no financial support for the research, authorship, and/or publication of this article.

Declaration of conflicting interests

The authors declared no potential conflicts of interest with respect to the research, authorship, and/or publication of this article.

References

Jiang

Huang

, et al. Analog-to-digital converter design exploration for compute-in-memory accelerators. IEEE Des Test 2021; 39(2): 48–55.

Naghizade

Saghaei

. An ultra-fast optical analog-to-digital converter using nonlinear X-shaped photonic crystal ring resonators. Opt Quant Electron 2021; 53(3): 149–153.

Aryavalli

SNG

Kumar

. Futuristic vigilance: empowering chipko movement with cyber-savvy IoT to safeguard forests. Arch Adv Enginee Sci 2023; 1(8): 1–16.

Gazman

. A new criterion for the ESG model. Gre Low-Carb Eco 2023; 1(1): 22–27.

Chen

Cui

Zhang

, et al. A survey on analog-to-digital converter integrated circuits for miniaturized high resolution ultrasonic imaging system. Micromachines 2022; 13(1): 114–127.

Pazhouhandeh

Chang

Valiante

, et al. Track-and-zoom neural analog-to-digital converter with blind stimulation artifact rejection. IEEE J Solid State Circ 2020; 55(7): 1984–1997.

Gielen

GGE

Hernandez

Rombouts

. Time-encoding analog-to-digital converters: bridging the analog gap to advanced digital cmos-part 1: basic principles. IEEE Solid-State Circuits Mag 2020; 12(2): 47–55.

Mulleti

Reznitskiy

Savariego

, et al. A hardware prototype of wideband high‐dynamic range analog‐to‐digital converter. IET Circuits, Devices Syst 2023; 17(4): 181–192.

Liang

Liu

, et al. 625kHz-BW, 79.3 dB-SNDR second-order noise-shaping SAR ADC using high-efficiency error-feedback structure. IEEE Transactions on Circuits and Systems II: Express Briefs 2021; 69(3): 859–863.

10.

Miki

Miura

Sonoda

, et al. A random interrupt dithering SAR technique for secure ADC against reference-charge side-channel attack. IEEE Trans Circuits Syst II 2019; 67(1): 14–18.

11.

Tang

Yang

Zhao

, et al. 13.5-ENOB, 107-μW noise-shaping SAR ADC with PVT-robust closed-loop dynamic amplifier. IEEE J Solid State Circ 2020; 55(12): 3248–3259.

12.

Jiang

Guo

, et al. A wideband front-end with integrated high-voltage assisted input buffer for high-speed ADC. IEICE Electron Express 2024; 21(24): 20240640–20240644.

13.

Huang

Liu

Wang

. Design of TID-tolerant ADCs in multivoltage domain based on body effect. IEEE Trans Nucl Sci 2023; 70(10): 2278–2284.

14.

Nguyen

Schembari

Staszewski

. Exploring speed maximization of frequency-to-digital conversion for ultra-low-voltage VCO-based ADCs. IEEE Trans Circ Syst I 2022; 70(3): 1043–1056.

15.

Zhang

Ning

, et al. A high area-efficiency 14-bit SAR ADC with hybrid capacitor DAC for array sensors. IEEE Trans Circ Syst I 2020; 67(12): 4396–4408.

16.

Hsieh

. A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC with opamp-less time-domain integrator. IEEE J Solid State Circ 2019; 54(6): 1648–1656.

17.

Ramkaj

Ramos

JCP

Pelgrom

MJM

, et al. A 5-GS/s 158.6-mW 9.4-ENOB passive-sampling time-interleaved three-stage pipelined-SAR ADC with analog–digital corrections in 28-nm CMOS. IEEE J Solid State Circ 2020; 55(6): 1553–1564.

18.

Bankman

Zheng

, et al. Understanding metastability in SAR ADCs: part II: asynchronous. IEEE Solid-State Circuits Mag 2019; 11(3): 16–32.

19.

Gielen

GGE

Hernandez

Rombouts

. Time-encoding analog-to-digital converters: bridging the analog gap to advanced digital cmos? Part 2: architectures and circuits. IEEE Solid-State Circuits Mag 2020; 12(3): 18–27.

20.

Shi

Yuan

Huang

, et al. Bias controller of Mach–Zehnder modulator for electro-optic analog-to-digital converter. Micromachines 2019; 10(12): 800–809.

21.

Sani

Khosroabadi

Nasserian

. High performance of an all-optical two-bit analog-to-digital converter based on Kerr effect nonlinear nanocavities. Appl Opt 2020; 59(4): 1049–1057.

22.

Fahmy

Zorkany

. Design of a memristor-based digital to analog converter (DAC). Electronics 2021; 10(5): 622–629.

23.

Long

Chen

Zhou

. Development of AR experiment on electric-thermal effect by open framework with simulation-based asset and user-defined input. Artif Intell Appl 2023; 1(1): 52–57.